Cypress CYV15G0404RB Rx Pll, Biststart, Bistwait, Bistdatacompare 000, Bistlastbad, Bistlastgood

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CYV15G0404RB

Figure 2. Receive BIST State Machine

		Monitor Data			Receive BIST
		Received	{BISTSTx, RXDx[0],		Detected LOW		RX PLL
				RXDx[1]} =		Out of Lock
				RXDx[1]} =		Out of Lock
			BIST_START (101)

{BISTSTx, RXDx[0], RXDx[1]} =
BIST_WAIT (111)
		Start of
	No	BIST Detected
	Yes, {BISTSTx, RXDx[0], RXDx[1]} =
	BIST_DATA_COMPARE (000, 001)
		Compare
		Next Character
	Mismatch
				Match	{BISTSTx, RXDx[0], RXDx[1]} =
Yes	Auto-Abort			Match	BIST_DATA_COMPARE (000, 001)
	Auto-Abort
	Condition
	Condition
	No
	End-of-BIST			End-of-BIST	No
	State			State
Yes, {BISTSTx, RXDx[0], RXDx[1]} =			Yes, {BISTSTx, RXDx[0], RXDx[1]} =
	BIST_LAST_BAD (100)		Yes, {BISTSTx, RXDx[0], RXDx[1]} =
	BIST_LAST_BAD (100)			BIST_LAST_GOOD (010)
				BIST_LAST_GOOD (010)
	No, {BISTSTx, RXDx[0], RXDx[1]} =
		BIST_ERROR (110)

Document #: 38-02102 Rev. *C

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Contents Features Functional DescriptionCypress Semiconductor Corporation CYV15G0404RB Deserializing Reclocker Logic Block Diagram Reclocking Deserializer Path Block Diagram Clock Device Configuration and Control Block Diagram = Internal SignalPin Configuration Top View1 Pin Configuration Bottom View1 Receive Path Clock Signals Device Control SignalsAsynchronous Device Reset Device Configuration and Control Bus Signals Name IO Characteristics Signal DescriptionLink Fault Indication Output Control Write Enable .Receive Channel Power Control Internal Device Configuration LatchesSignal Detect Amplitude Select Receive Bist DisabledCYV15G0404RB HOTLink II Operation CYV15G0404RB Receive Data PathHigh Clock/Data RecoveryLOW ReclockerPower Control Device Configuration and Control InterfaceLatch Types Force Global Enable FunctionMask Function Static Latch ValuesDevice Configuration Strategy Device Control Latch Configuration Table DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0Jtag Support Receive Bist Status BitsLevel Select Inputs Bistwait RX PLLBiststart Bistdatacompare 000CYV15G0404RB DC Electrical Characteristics Operating Range Maximum RatingsCYV15G0404RB DC Electrical Characteristics AC Test Loads and WaveformsCYV15G0404RB AC Electrical Characteristics Parameter Description Min Max Unit CYV15G0404RB Device PLL CharacteristicsCapacitance14 Parameter Description Test Conditions Max UnitBus Configuration Write Timing Receive Interface Read Timing RXRATEx =Lvttl in PU VCC PowerCML CML OUTRXDB8 Lvttl OUT ROUTB2+ CML OUTTDI Lvttl in PU TMS Lvttl in PUSpeed Ordering Code Package Package Type Operating Package DiagramOrdering Information RangeSUA Document HistoryFRE AGT