Cypress CYV15G0404RB manual Reclocking Deserializer Path Block Diagram

CYV15G0404RB

Reclocking Deserializer Path Block Diagram

TRGRATEA

TRGCLKA x2

SDASEL[2..1]A[1:0]

LDTDEN

	Receive
INSELA	Signal				LFSRBIST
	Monitor		Shifter
				10		10
INA2+	Data
INA1+
INA1–	Clock &
INA2–	Recovery
ULCA	PLL
SPDSELA			RXBISTA[1:0]
RXPLLPDA
				RXRATEA
	Recovered Character Clock	Recovered Serial Data
	Reclocker			ROE[2..1]A
	Output PLL
	Clock Multiplier A
RECLKOA	Character-Rate Clock A
REPDOA

					= Internal Signal
									RESET
	JTAG						TRST
								TMS
Boundary								TCLK
		Scan
								TDI
Controller
								TDO
							LFIA
Output Register
				10		RXDA[9:0]
						BISTSTA
						RXCLKA+
			⎟2
		RXCLKA–

ROE[2..1]A

Register	ROUTA1+
	ROUTA1–
	ROUTA2+
	ROUTA2–

TRGRATEB
TRGCLKB	x2
SDASEL[2..1]B[1:0]
LDTDEN
	Receive
INSELB	Signal				LFSRBIST
	Monitor		Shifter
				10		10
INB2+	Data
INB1+
INB1–	Clock &
INB2–	Recovery
ULCB	PLL
SPDSELB			RXBISTB[1:0]
RXPLLPDB
				RXRATEB
	Recovered Character Clock	Recovered Serial Data
	Reclocker			ROE[2..1]B
	Output PLL
	Clock Multiplier B
RECLKOB	Character-Rate Clock B
REPDOB

Output Register

Register

			LFIB
		RXDB[9:0]
10
		BISTSTB
		RXCLKB+
	⎟2
RXCLKB–

ROE[2..1]B

ROUTB1+

ROUTB1–

ROUTB2+

ROUTB2–

Document #: 38-02102 Rev. *C Page 3 of 27

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