Cypress CYV15G0404RB manual PLL Characteristics, Capacitance14

Page 22

CYV15G0404RB

CYV15G0404RB AC Electrical Characteristics (continued)

Parameter

 

 

Description

 

Min

Max

Unit

 

 

 

 

 

 

CYV15G0404RB Device

RESET

Characteristics Over the Operating Range

 

 

 

 

 

 

 

 

 

tRST

Device RESET Pulse Width

 

30

 

ns

CYV15G0404RB Reclocker Serial Output Characteristics Over the Operating Range

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

Description

Condition

Min.

Max.

Unit

 

 

 

 

 

 

tB

Bit Time

 

5128

660

ps

tRISE[14]

CML Output Rise Time 2080% (CML Test Load)

SPDSELx = HIGH

50

270

ps

 

 

 

 

SPDSELx = MID

100

500

ps

 

 

 

 

 

 

 

 

 

 

 

 

SPDSELx =LOW

180

1000

ps

 

 

 

 

 

 

tFALL[14]

CML Output Fall Time 8020% (CML Test Load)

SPDSELx = HIGH

50

270

ps

 

 

 

 

SPDSELx = MID

100

500

ps

 

 

 

 

 

 

 

 

 

 

 

 

SPDSELx =LOW

180

1000

ps

 

 

 

 

 

 

 

 

PLL Characteristics

Parameter

Description

Condition

Min

Typ

Max

Unit

 

 

 

 

 

 

 

CYV15G0404RB Reclocker Output PLL Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

tJRGENSD[14, 22]

Reclocker Jitter Generation - SD Data Rate

TRGCLKx = 27 MHz

 

133

 

ps

tJRGENHD[14, 22]

Reclocker Jitter Generation - HD Data Rate

TRGCLKx = 148.5 MHz

 

107

 

ps

CYV15G0404RB Receive PLL Characteristics Over the Operating Range

 

 

 

 

 

 

 

 

 

 

 

tRXLOCK

Receive PLL Lock to Input Data Stream (cold start)

 

 

 

376k

UI

 

Receive PLL Lock to Input Data Stream

 

 

 

376k

UI

 

 

 

 

 

 

 

tRXUNLOCK

Receive PLL Unlock Rate

 

 

 

46

UI

Capacitance[14]

Parameter

Description

Test Conditions

Max

Unit

 

 

 

 

 

CINTTL

TTL Input Capacitance

TA = 25°C, f0 = 1 MHz, VCC = 3.3V

7

pF

CINPECL

PECL input Capacitance

TA = 25°C, f0 = 1 MHz, VCC = 3.3V

4

pF

Note

22.Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide bandwidth digital sampling oscilloscope. The measurement was recorded after 10,000 histogram hits, time referenced to REFCLKx± of the transmit channel.

Document #: 38-02102 Rev. *C

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Contents Functional Description FeaturesCypress Semiconductor Corporation CYV15G0404RB Deserializing Reclocker Logic Block Diagram Reclocking Deserializer Path Block Diagram Clock Device Configuration and Control Block Diagram = Internal SignalPin Configuration Top View1 Pin Configuration Bottom View1 Device Control Signals Receive Path Clock SignalsAsynchronous Device Reset Device Configuration and Control Bus Signals Name IO Characteristics Signal DescriptionLink Fault Indication Output Control Write Enable .Receive Channel Power Control Internal Device Configuration LatchesSignal Detect Amplitude Select Receive Bist DisabledCYV15G0404RB HOTLink II Operation CYV15G0404RB Receive Data PathHigh Clock/Data RecoveryLOW ReclockerPower Control Device Configuration and Control InterfaceLatch Types Force Global Enable FunctionMask Function Static Latch ValuesDevice Configuration Strategy Device Control Latch Configuration Table DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0Receive Bist Status Bits Jtag SupportLevel Select Inputs Bistwait RX PLLBiststart Bistdatacompare 000CYV15G0404RB DC Electrical Characteristics Operating Range Maximum RatingsCYV15G0404RB DC Electrical Characteristics AC Test Loads and WaveformsCYV15G0404RB AC Electrical Characteristics Parameter Description Min Max Unit CYV15G0404RB Device PLL CharacteristicsCapacitance14 Parameter Description Test Conditions Max UnitBus Configuration Write Timing Receive Interface Read Timing RXRATEx =Lvttl in PU VCC PowerCML CML OUTRXDB8 Lvttl OUT ROUTB2+ CML OUTTDI Lvttl in PU TMS Lvttl in PUSpeed Ordering Code Package Package Type Operating Package DiagramOrdering Information RangeSUA Document HistoryFRE AGT