Cypress manual CYV15G0404RB Deserializing Reclocker Logic Block Diagram

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CYV15G0404RB

Figure 1. HOTLink II™ System Connections

Video Coprocessor

10

10

10

10

Independent

Channel

CYV15G0403TB

Serializer

Reclocked

Outputs

Serial Links

Reclocked

Outputs

Independent

Channel

CYV15G0404RB

Reclocking Deserializer

10

10

10

10

Video Coprocessor

CYV15G0404RB Deserializing Reclocker Logic Block Diagram

	RXDA[9:0]		TRGCLKA±
	x10

	RXDB[9:0]		TRGCLKB±
	x10

	RXDC[9:0]		TRGCLKC±
	x10

	RXDD[9:0]		TRGCLKD±
	x10

Deserializer

Reclocker RX

Deserializer

Reclocker RX

Deserializer

Reclocker RX

Deserializer

Reclocker RX

ROUTA1± ROUTA2±

INA1± INA2±

ROUTB1± ROUTB2±

INB1± INB2±

ROUTC1± ROUTC2±

INC1± INC2±

ROUTD1± ROUTD2±

IND1± IND2±

Document #: 38-02102 Rev. *C

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Contents Cypress Semiconductor Corporation FeaturesFunctional Description CYV15G0404RB Deserializing Reclocker Logic Block Diagram Reclocking Deserializer Path Block Diagram Clock Device Configuration and Control Block Diagram = Internal SignalPin Configuration Top View1 Pin Configuration Bottom View1 Asynchronous Device Reset Receive Path Clock SignalsDevice Control Signals Device Configuration and Control Bus Signals Name IO Characteristics Signal DescriptionLink Fault Indication Output Control Write Enable .Receive Channel Power Control Internal Device Configuration LatchesSignal Detect Amplitude Select Receive Bist DisabledCYV15G0404RB HOTLink II Operation CYV15G0404RB Receive Data PathHigh Clock/Data RecoveryLOW ReclockerPower Control Device Configuration and Control InterfaceLatch Types Force Global Enable FunctionMask Function Static Latch ValuesDevice Configuration Strategy Device Control Latch Configuration Table DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0Level Select Inputs Jtag SupportReceive Bist Status Bits Bistwait RX PLLBiststart Bistdatacompare 000CYV15G0404RB DC Electrical Characteristics Operating Range Maximum RatingsCYV15G0404RB DC Electrical Characteristics AC Test Loads and WaveformsCYV15G0404RB AC Electrical Characteristics Parameter Description Min Max Unit CYV15G0404RB Device PLL CharacteristicsCapacitance14 Parameter Description Test Conditions Max UnitBus Configuration Write Timing Receive Interface Read Timing RXRATEx =Lvttl in PU VCC PowerCML CML OUTRXDB8 Lvttl OUT ROUTB2+ CML OUTTDI Lvttl in PU TMS Lvttl in PUSpeed Ordering Code Package Package Type Operating Package DiagramOrdering Information RangeSUA Document HistoryFRE AGT