Cypress SL811HS manual Pin Plcc Physical Connections, Pin Plcc Pin Layout

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SL811HS

Physical Connections

These parts are offered in both a 28-pin PLCC package and a 48-pin TQFP package. The 28-pin PLCC packages are the SL811HS and SL811HS-JCT. The 48-pin TQFP packages is the SL811HST-AXC.

28-Pin PLCC Physical Connections

28-Pin PLCC Pin Layout

*See Table 35 on page 21 for Pin and Signal Description for Pins 2 and 3 in Host Mode.

Figure 4. 28-pin PLCC USB Host/Slave Controller — Pin Layout

nWR

nCS

VDD2

DATA+

DATA-

Gnd

28-Pin PLCC Mechanical Dimensions

	nRD			nDACK*		VDD1
			nDRQ*		A0		M/S D7
			nDRQ*
4										26
4										26

	5		3	2	1	28		27	25			D6
	5								24			D5
	6								24			D5
	7			28 PLCC					23			D4
	7								23			D4
	8								22			Gnd
	8								22			Gnd
	9								21			D3
	10								20			D2
	11	13		14	15	16	17		19			D1
12											18
12											18

VDD1				X2		INTRQ			D0
		CLK/X1			nRST		Gnd

Document 38-08008 Rev. *D

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Contents Master/Slave Controller FeaturesIntroduction Cypress Semiconductor CorporationData Port, Microprocessor Interface DMA Controller slave mode onlyAuto Address Increment Mode Interrupt ControllerFrequency Tolerance SL811HS RegistersMHz Crystals USB TransceiverRegister Values on Power Up and Reset USB Control RegistersSL811HS Host Control Registers ISO Bit Position Bit Name FunctionHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 PID Type HBL7 HBL6HBL4 HBL3 HBL2 HBL1 HBL0 D7-D4DA6 DA5 DA4 DA3 DA2 DA1 DA0 HTC7HTC2 DA7Control Register 1 Address 05h Bit Low-power Modes Bit 6 Control Register, Address 05hUSB Reset Sequence Control Register 1 Address 05h Bits 3Done Interrupt Enable Register Address 06hUSB-B USB-A USB-B DoneUSB-B Interrupt Status Register Address 0Dh BitValue of the Data+ pin Revision Reserved Bit Position Bit Name FunctionSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoints 0-3 Register Addresses Register Name Miscellaneous register addressesEndpoint Registers Endpoints 0-3 Register AddressesNext Data Set Endpoint Control RegistersSequence EPxLEN1 EPxLEN0Current Data Set Register Reserved OverflowTransmission Acknowledge Control Register 0Fh SOF Low Byte RegisterControl Register 1 Address 05h Stbyd SpselStbyd USBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 USB Address Register, Address 07h. This registerUSB Address Register Address 07h Interrupt Status Register Address 0DhReserved Master/Slave Current Data Set Register Address 0EhControl Register 2 Address 0Fh Bit SL811HSPin Plcc Physical Connections Pin Plcc Mechanical DimensionsPhysical Connections Pin Plcc Pin LayoutDiagram below illustrates a simple +3.3V voltage source Package Markings 28-pin PlccPin Tqfp Physical Connections Pin Tqfp AXC Pin Layout48/28-Pin USB Host Controller Pins Description Power for USB Transceivers . V DD1 may be connected to V DDData 7. Microprocessor Data/Address Bus Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 6. Microprocessor Data/Address Bus Buffer or registerYyww Xxxx Package Markings 48-Pin TqfpElectrical Specifications DC Characteristics Parameter Description Min Typ Max Parameter Description Min Typ Max Bus Interface Timing RequirementsWrite Cycle NWR HighRead Cycle DMA Write Cycle DMA Write CycleNRst Pulse width Reset TimingDMA Read Cycle NRst High to nRD or nWR activeCLOCKClock TimingTIMING Parameter Description Min Typ Max Package DiagramsOrdering Information Part Number Package TypeLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Issue Date Orig. Description of Change Document HistoryREV ECN no