Cypress manual HTC7, HTC2, DA6 DA5 DA4 DA3 DA2 DA1 DA0, DA7, SL811HS Control Registers

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SL811HS

USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [Address = 04h, 0Ch]. This register has two different functions depending on whether it is read or written. When read, this register contains the number of bytes remaining (from Host Base Length value) after a packet is transferred. For example, if the Base Length register is set to 0x040 and an IN Token was sent to the peripheral device. If, after the transfer is complete, the value of the Host Transfer Count is 0x10, the number of bytes actually transferred is 0x30. This is considered as an underflow indication.

Table 8. USB-A / USB-B Host Transfer Count Register when READ [Address 04h,						0Ch]

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit	2	Bit 1	Bit 0
HTC7	HTC6	HTC5	HTC4	HTC3	HTC2		HTC1	HTC0

When written, this register contains the USB Device Address with which the Host communicates.

Table 9. USB-A / USB-B USB Address when WRITTEN [Address 04h, 0Ch]

Bit 7	Bit 6	Bit 5		Bit 4		Bit3	Bit 2	Bit 1	Bit 0
0	DA6	DA5		DA4		DA3	DA2	DA1	DA0

DA6-DA0	Device address, up to 127 devices can be addressed.
DA7	Reserved bit must be set to zero.

SL811HS Control Registers

The next set of registers are the Control registers and control more of the operation of the chip instead of USB packet type of transfers. Table 10 is a summary of the control registers.

Table 10. SL811HS Control Registers Summary

Register Name SL811H	SL811HS (hex) Address
Control Register 1	05h

Interrupt Enable Register	06h

Reserved Register	07h

Status Register	0Dh

SOF Counter LOW (Write)/HW Revision Register (Read)	0Eh

SOF Counter HIGH and Control Register 2	0Fh

Memory Buffer	10h-FFh

Document 38-08008 Rev. *D

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Contents Cypress Semiconductor Corporation FeaturesIntroduction Master/Slave ControllerInterrupt Controller DMA Controller slave mode onlyAuto Address Increment Mode Data Port, Microprocessor InterfaceUSB Transceiver SL811HS RegistersMHz Crystals Frequency ToleranceUSB Control Registers Register Values on Power Up and ResetSL811HS Host Control Registers Bit Position Bit Name Function ISOHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 D7-D4 HBL7 HBL6HBL4 HBL3 HBL2 HBL1 HBL0 PID TypeDA7 HTC7HTC2 DA6 DA5 DA4 DA3 DA2 DA1 DA0Control Register 1 Address 05h Bits 3 Low-power Modes Bit 6 Control Register, Address 05hUSB Reset Sequence Control Register 1 Address 05h BitUSB-B Done Interrupt Enable Register Address 06hUSB-B USB-A DoneRevision Reserved Bit Position Bit Name Function Interrupt Status Register Address 0Dh BitValue of the Data+ pin USB-BSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoints 0-3 Register Addresses Register Name Miscellaneous register addressesEndpoint Registers Endpoints 0-3 Register AddressesEPxLEN1 EPxLEN0 Endpoint Control RegistersSequence Next Data SetControl Register 0Fh SOF Low Byte Register Reserved OverflowTransmission Acknowledge Current Data Set RegisterStbyd Spsel Control Register 1 Address 05hStbyd Interrupt Status Register Address 0Dh USB Address Register, Address 07h. This registerUSB Address Register Address 07h USBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0SL811HS Current Data Set Register Address 0EhControl Register 2 Address 0Fh Bit Reserved Master/SlavePin Plcc Pin Layout Pin Plcc Mechanical DimensionsPhysical Connections Pin Plcc Physical ConnectionsPackage Markings 28-pin Plcc Diagram below illustrates a simple +3.3V voltage sourcePin Tqfp AXC Pin Layout Pin Tqfp Physical ConnectionsPower for USB Transceivers . V DD1 may be connected to V DD 48/28-Pin USB Host Controller Pins DescriptionBuffer or register Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 6. Microprocessor Data/Address Bus Data 7. Microprocessor Data/Address BusPackage Markings 48-Pin Tqfp Yyww XxxxElectrical Specifications DC Characteristics Parameter Description Min Typ Max NWR High Bus Interface Timing RequirementsWrite Cycle Parameter Description Min Typ MaxRead Cycle DMA Write Cycle DMA Write CycleNRst High to nRD or nWR active Reset TimingDMA Read Cycle NRst Pulse widthPart Number Package Type Package DiagramsOrdering Information CLOCKClock TimingTIMING Parameter Description Min Typ MaxLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Document History Issue Date Orig. Description of ChangeREV ECN no