Cypress SL811HS manual Control Register 1 Address 05h, Stbyd Spsel

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SL811HS

Control Register 1, Address [05h]. The Control register enables or disables USB transfers and DMA operations with control bits.

Table 28. Control Register 1 [Address 05h]

7

6

5

4

3

2

1

0

Reserved

STBYD

SPSEL

J-K1

J-K0

DMA Dir

DMA Enable

USB Enable

Bit Position

Bit Name

Function

7

Reserved

Reserved bit - must be set to '0'.

6

STBYD

XCVR Power Control. ‘1’ sets XCVR to low power. For normal operation set this bit to ‘0’.

Suspend mode is entered if bit 6 = ‘1’ and bit ‘0’ (USB Enable) = ‘0’.

5

SPSEL

Speed Select. ‘0’ selects full speed. ‘1’ selects low speed (also see Table 34 on page 17).

4

J-K1

J-K1 and J-K0 force state control bits are used to generate various USB bus conditions.

Forcing K-state is used for Peripheral device remote wake-up, Resume, and other modes.

3

J-K0

These two bits are set to zero on power up, see Table 29 for functions.

2

DMA Dir

DMA Transfer Direction. Set equal to ‘1’ for DMA READ cycles from SL811HS. Set equal to

‘0’ for DMA WRITE cycles.

1

DMA Enable

Enable DMA operation when equal to ‘1’. Disable = ‘0’. DMA is initiated when DMA Count

High is written.

0

USB Enable

Overall Enable for Transfers. ‘1’ enables and’ ‘0 disables. Set this bit to ‘1’ to enable USB

communication. Default at power up = ‘0’

Table 29. J-K Force-state Control Bits

JK-Force State

USB Engine Reset

Function

0

0

Normal operating mode

0

1

Force SE0, D+ and D– are set low

1

0

Force K-State, D– set high, D+ set low

1

1

Force J-State, D+ set high, D– set low

Document 38-08008 Rev. *D

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Contents Cypress Semiconductor Corporation FeaturesIntroduction Master/Slave ControllerInterrupt Controller DMA Controller slave mode onlyAuto Address Increment Mode Data Port, Microprocessor InterfaceUSB Transceiver SL811HS RegistersMHz Crystals Frequency ToleranceRegister Values on Power Up and Reset USB Control RegistersSL811HS Host Control Registers ISO Bit Position Bit Name FunctionHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 D7-D4 HBL7 HBL6HBL4 HBL3 HBL2 HBL1 HBL0 PID TypeDA7 HTC7HTC2 DA6 DA5 DA4 DA3 DA2 DA1 DA0Control Register 1 Address 05h Bits 3 Low-power Modes Bit 6 Control Register, Address 05hUSB Reset Sequence Control Register 1 Address 05h BitUSB-B Done Interrupt Enable Register Address 06hUSB-B USB-A DoneRevision Reserved Bit Position Bit Name Function Interrupt Status Register Address 0Dh BitValue of the Data+ pin USB-BSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoints 0-3 Register Addresses Register Name Miscellaneous register addressesEndpoint Registers Endpoints 0-3 Register AddressesEPxLEN1 EPxLEN0 Endpoint Control RegistersSequence Next Data SetControl Register 0Fh SOF Low Byte Register Reserved OverflowTransmission Acknowledge Current Data Set RegisterControl Register 1 Address 05h Stbyd SpselStbyd Interrupt Status Register Address 0Dh USB Address Register, Address 07h. This registerUSB Address Register Address 07h USBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0SL811HS Current Data Set Register Address 0EhControl Register 2 Address 0Fh Bit Reserved Master/SlavePin Plcc Pin Layout Pin Plcc Mechanical DimensionsPhysical Connections Pin Plcc Physical ConnectionsPackage Markings 28-pin Plcc Diagram below illustrates a simple +3.3V voltage sourcePin Tqfp AXC Pin Layout Pin Tqfp Physical ConnectionsPower for USB Transceivers . V DD1 may be connected to V DD 48/28-Pin USB Host Controller Pins DescriptionBuffer or register Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 6. Microprocessor Data/Address Bus Data 7. Microprocessor Data/Address BusPackage Markings 48-Pin Tqfp Yyww XxxxElectrical Specifications DC Characteristics Parameter Description Min Typ Max NWR High Bus Interface Timing RequirementsWrite Cycle Parameter Description Min Typ MaxRead Cycle DMA Write Cycle DMA Write CycleNRst High to nRD or nWR active Reset TimingDMA Read Cycle NRst Pulse widthPart Number Package Type Package DiagramsOrdering Information CLOCKClock TimingTIMING Parameter Description Min Typ MaxLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Issue Date Orig. Description of Change Document HistoryREV ECN no