Cypress SL811HS manual 48/28-Pin USB Host Controller Pins Description

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SL811HS

48/28-Pin USB Host Controller Pins Description

The SL811HST-AXC is packaged in a 48-pin TQFP. The SL811HS and SL811HS-JCT packages are 28-pin PLCC’s. These devices require a 3.3 VDC power source. The 48-Pin TQFP requires an external 12 or 48 MHz crystal or clock.

Table 35. 48/28-Pin TQFP AXC Pin Assignments and Definitions

48-Pin TQFP

28-Pin PLCC

Pin Type

Pin Name

Pin Description

AXC Pin No.

Pin No.

 

 

 

1

NC

NC

No connection.

 

 

 

 

 

2

NC

NC

No connection.

 

 

 

 

 

3

5

IN

nWR

Write Strobe Input. An active LOW input used with nCS to write

 

 

 

 

to registers/data memory.

4

6

IN

nCS

Active LOW 48-Pin TQFP Chip select. Used with nRD and nWr

 

 

 

 

when accessing the 48-Pin TQFP.

5[5]

7[6]

IN

CM

Clock Multiply. Select 12 MHz/48 MHz Clock Source.

6

8

VDD1

+3.3 VDC

Power for USB Transceivers. VDD1 may be connected to VDD.

7

9

BIDIR

DATA +

USB Differential Data Signal HIGH Side.

 

 

 

 

 

8

10

BIDIR

DATA -

USB Differential Data Signal LOW Side.

 

 

 

 

 

9

11

GND

USB GND

Ground Connection for USB.

 

 

 

 

 

10

NC

NC

No connection.

 

 

 

 

 

11

NC

NC

No connection.

 

 

 

 

 

12

NC

NC

No connection.

 

 

 

 

 

13

NC

NC

No connection.

 

 

 

 

 

14

NC

NC

No connection.

 

 

 

 

 

15[7]

12

VDD

+3.3 VDC

Device VDD Power.

16

13

IN

CLK/X1

Clock or External Crystal X1 connection. The X1/X2 Clock

 

 

 

 

requires external 12 or 48 MHz matching crystal or clock source.

17

14

OUT

X2

External Crystal X2 connection.

 

 

 

 

 

18

15

IN

nRST

Device active low reset input.

 

 

 

 

 

19

16

OUT

INTRQ

Active HIGH Interrupt Request output to external controller.

 

 

 

 

 

20

17

GND

GND

Device Ground.

 

 

 

 

 

21

18

BIDIR

D0

Data 0. Microprocessor Data/Address Bus.

22

NC

NC

No connection.

 

 

 

 

 

23

NC

NC

No connection.

 

 

 

 

 

24

NC

NC

No connection.

 

 

 

 

 

25

NC

NC

No connection.

 

 

 

 

 

26

NC

NC

No connection.

 

 

 

 

 

27

19

BIDIR

D1

Data 1. Microprocessor Data/Address Bus.

28

20

BIDIR

D2

Data 2. Microprocessor Data/Address Bus.

 

 

 

 

 

29

21

BIDIR

D3

Data 3. Microprocessor Data/Address Bus.

 

 

 

 

 

30

22

GND

GND

Device Ground.

 

 

 

 

 

31

23

BIDIR

D4

Data 4. Microprocessor Data/Address Bus.

 

 

 

 

 

32

24

BIDIR

D5

Data 5. Microprocessor Data/Address Bus.

 

 

 

 

 

Notes

5.The CM Clock Multiplier pin must be tied HIGH for a 12 MHz clock source and tied to ground for a 48 MHz clock source.

6.The CM Clock Multiplier pin must be tied HIGH for a 12 MHz clock source and tied to ground for a 48 MHz clock source. In 28-pin PLCC’s, this pin is designated as an ALE input pin.

7.VDD can be derived from the USB supply. See Figure 5 on page 19.

Document 38-08008 Rev. *D

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Contents Introduction FeaturesMaster/Slave Controller Cypress Semiconductor CorporationAuto Address Increment Mode DMA Controller slave mode onlyData Port, Microprocessor Interface Interrupt ControllerMHz Crystals SL811HS RegistersFrequency Tolerance USB TransceiverRegister Values on Power Up and Reset USB Control RegistersSL811HS Host Control Registers ISO Bit Position Bit Name FunctionHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 HBL4 HBL3 HBL2 HBL1 HBL0 HBL7 HBL6PID Type D7-D4HTC2 HTC7DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7USB Reset Sequence Low-power Modes Bit 6 Control Register, Address 05hControl Register 1 Address 05h Bit Control Register 1 Address 05h Bits 3USB-B USB-A Interrupt Enable Register Address 06hDone USB-B DoneValue of the Data+ pin Interrupt Status Register Address 0Dh BitUSB-B Revision Reserved Bit Position Bit Name FunctionSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoint Registers Register Name Miscellaneous register addressesEndpoints 0-3 Register Addresses Endpoints 0-3 Register AddressesSequence Endpoint Control RegistersNext Data Set EPxLEN1 EPxLEN0Transmission Acknowledge Reserved OverflowCurrent Data Set Register Control Register 0Fh SOF Low Byte RegisterControl Register 1 Address 05h Stbyd SpselStbyd USB Address Register Address 07h USB Address Register, Address 07h. This registerUSBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 Interrupt Status Register Address 0DhControl Register 2 Address 0Fh Bit Current Data Set Register Address 0EhReserved Master/Slave SL811HSPhysical Connections Pin Plcc Mechanical DimensionsPin Plcc Physical Connections Pin Plcc Pin LayoutPackage Markings 28-pin Plcc Diagram below illustrates a simple +3.3V voltage sourcePin Tqfp AXC Pin Layout Pin Tqfp Physical ConnectionsPower for USB Transceivers . V DD1 may be connected to V DD 48/28-Pin USB Host Controller Pins DescriptionData 6. Microprocessor Data/Address Bus Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 7. Microprocessor Data/Address Bus Buffer or registerPackage Markings 48-Pin Tqfp Yyww XxxxElectrical Specifications DC Characteristics Parameter Description Min Typ Max Write Cycle Bus Interface Timing RequirementsParameter Description Min Typ Max NWR HighRead Cycle DMA Write Cycle DMA Write CycleDMA Read Cycle Reset TimingNRst Pulse width NRst High to nRD or nWR activeOrdering Information Package DiagramsCLOCKClock TimingTIMING Parameter Description Min Typ Max Part Number Package TypeLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Issue Date Orig. Description of Change Document HistoryREV ECN no