Cypress SL811HS manual Pin Tqfp Physical Connections, Pin Tqfp AXC Pin Layout

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SL811HS

48-Pin TQFP Physical Connections

48-Pin TQFP AXC Pin Layout

Figure 6. 48-Pin TQFP AXC USB Host/Slave Controller Pin Layout

NC[4]

NC 48 NC

nWR nCS

VDD1

Data+

Data-

USBGnd

NC 12

NC	nRD nDACK* VDD		D7	NC
NC	nDRQ*	A0	M/S	NC

37 36

48-Pin TQFP

NC Clk/X1

nRST GND

VDD

INTRQ

GND

*See Table 35 on page 21 for Pin and Signal Description for Pins 43 and 44 in Host Mode. 48-Pin TQFP Mechanical Dimensions

Note

4. NC. Indicates No Connection. NC Pins must be left unconnected.

Document 38-08008 Rev. *D

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Contents Features IntroductionMaster/Slave Controller Cypress Semiconductor CorporationDMA Controller slave mode only Auto Address Increment ModeData Port, Microprocessor Interface Interrupt ControllerSL811HS Registers MHz CrystalsFrequency Tolerance USB TransceiverSL811HS Host Control Registers Register Values on Power Up and ResetUSB Control Registers HBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 ISOBit Position Bit Name Function HBL7 HBL6 HBL4 HBL3 HBL2 HBL1 HBL0PID Type D7-D4HTC7 HTC2DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7Low-power Modes Bit 6 Control Register, Address 05h USB Reset SequenceControl Register 1 Address 05h Bit Control Register 1 Address 05h Bits 3Interrupt Enable Register Address 06h USB-B USB-ADone USB-B DoneInterrupt Status Register Address 0Dh Bit Value of the Data+ pinUSB-B Revision Reserved Bit Position Bit Name FunctionSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Register Name Miscellaneous register addresses Endpoint RegistersEndpoints 0-3 Register Addresses Endpoints 0-3 Register AddressesEndpoint Control Registers SequenceNext Data Set EPxLEN1 EPxLEN0Reserved Overflow Transmission AcknowledgeCurrent Data Set Register Control Register 0Fh SOF Low Byte RegisterStbyd Control Register 1 Address 05hStbyd Spsel USB Address Register, Address 07h. This register USB Address Register Address 07hUSBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 Interrupt Status Register Address 0DhCurrent Data Set Register Address 0Eh Control Register 2 Address 0Fh BitReserved Master/Slave SL811HSPin Plcc Mechanical Dimensions Physical ConnectionsPin Plcc Physical Connections Pin Plcc Pin LayoutDiagram below illustrates a simple +3.3V voltage source Package Markings 28-pin PlccPin Tqfp Physical Connections Pin Tqfp AXC Pin Layout48/28-Pin USB Host Controller Pins Description Power for USB Transceivers . V DD1 may be connected to V DDMaster/Slave Mode Select. ’1’ selects Slave. ’0’ = Master Data 6. Microprocessor Data/Address BusData 7. Microprocessor Data/Address Bus Buffer or registerYyww Xxxx Package Markings 48-Pin TqfpElectrical Specifications DC Characteristics Parameter Description Min Typ Max Bus Interface Timing Requirements Write CycleParameter Description Min Typ Max NWR HighRead Cycle DMA Write Cycle DMA Write CycleReset Timing DMA Read CycleNRst Pulse width NRst High to nRD or nWR activePackage Diagrams Ordering InformationCLOCKClock TimingTIMING Parameter Description Min Typ Max Part Number Package TypeLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 REV ECN no Issue Date Orig. Description of ChangeDocument History