Cypress SL811HS manual Features, Introduction, Master/Slave Controller

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SL811HS

SL811HS Embedded USB Host/Slave Controller

Features

•First USB Host/Slave controller for embedded systems in the market with a standard microprocessor bus interface

•Supports both full speed (12 Mbps) and low speed (1.5 Mbps) USB transfer in both master and slave modes

•Conforms to USB Specification 1.1 for full- and low speed

•Operates as a single USB host or slave under software control

•Automatic detection of either low- or full speed devices

•8-bit bidirectional data, port I/O (DMA supported in slave mode)

•On-chip SIE and USB transceivers

•On-chip single root HUB support

•256-byte internal SRAM buffer

•Ping-pong buffers for improved performance

•Operates from 12 or 48 MHz crystal or oscillator (built-in DPLL)

•5V-tolerant interface

•Suspend/resume, wake up, and low-power modes are supported

•Auto-generation of SOF and CRC5/16

•Auto-address increment mode, saves memory READ/WRITE cycles

•Development kit including source code drivers is available

•3.3V power source, 0.35 micron CMOS technology

•Available in both a 28-pin PLCC package and a 48-pin TQFP package

Introduction

The SL811HS is an Embedded USB Host/Slave Controller capable of communicating in either full speed or low speed. The SL811HS interfaces to devices such as microprocessors, microcontrollers, DSPs, or directly to a variety of buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1.

The SL811HS incorporates USB Serial Interface functionality along with internal full or low speed transceivers. The SL811HS supports and operates in USB full speed mode at 12 Mbps, or in low speed mode at 1.5 Mbps. When in host mode, the SL811HS is the master and controls the USB bus and the devices that are connected to it. In peripheral mode, otherwise known as a slave device, the SL811HS operates as a variety of full- or low speed devices.

The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support to allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUs and many others. The SL811HS has 256-bytes of internal RAM which is used for control registers and data buffer.

The available package types offered are a 28-pin PLCC (SL811HS) and the lead-free packages are a 28-pin (SL811HS-JCT) and a 48-pin (SL811HST-AXC) package. All packages operate at 3.3 VDC. The I/O interface logic is 5V-tolerant.

Block Diagram

 

 

 

 

 

 

 

 

 

 

 

Master/Slave

 

 

 

 

 

 

 

 

Controller

 

INTERRUPT

 

INTR

 

 

 

 

 

 

CONTROLLER

 

 

 

 

 

 

 

 

 

D

 

SERIAL

256 Byte RAM

 

 

USB

 

 

 

 

 

+

BUFFERS

 

 

 

 

INTERFACE

 

 

nDRQ

D-

Root HUB

DMA

 

 

 

 

&

 

 

 

XCVRS

ENGINE

CONTROL

Interface

 

 

 

 

 

REGISTERS

 

nDACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

nWR

 

 

 

 

 

 

PROCESSOR

 

nRD

 

CLOCK

 

 

 

 

nCS

 

 

 

 

INTERFACE

 

 

 

 

 

 

nRST

 

GENERATOR

 

 

 

 

 

 

 

 

 

 

 

 

 

D0-7

 

X1

X2

 

 

 

 

 

 

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document 38-08008 Rev. *D

 

 

 

 

Revised February 2, 2007

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Contents Introduction FeaturesMaster/Slave Controller Cypress Semiconductor CorporationAuto Address Increment Mode DMA Controller slave mode onlyData Port, Microprocessor Interface Interrupt ControllerMHz Crystals SL811HS RegistersFrequency Tolerance USB TransceiverUSB Control Registers Register Values on Power Up and ResetSL811HS Host Control Registers Bit Position Bit Name Function ISOHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 HBL4 HBL3 HBL2 HBL1 HBL0 HBL7 HBL6PID Type D7-D4HTC2 HTC7DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7USB Reset Sequence Low-power Modes Bit 6 Control Register, Address 05hControl Register 1 Address 05h Bit Control Register 1 Address 05h Bits 3USB-B USB-A Interrupt Enable Register Address 06hDone USB-B DoneValue of the Data+ pin Interrupt Status Register Address 0Dh BitUSB-B Revision Reserved Bit Position Bit Name FunctionSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoint Registers Register Name Miscellaneous register addressesEndpoints 0-3 Register Addresses Endpoints 0-3 Register AddressesSequence Endpoint Control RegistersNext Data Set EPxLEN1 EPxLEN0Transmission Acknowledge Reserved OverflowCurrent Data Set Register Control Register 0Fh SOF Low Byte RegisterStbyd Spsel Control Register 1 Address 05hStbyd USB Address Register Address 07h USB Address Register, Address 07h. This registerUSBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 Interrupt Status Register Address 0DhControl Register 2 Address 0Fh Bit Current Data Set Register Address 0EhReserved Master/Slave SL811HSPhysical Connections Pin Plcc Mechanical DimensionsPin Plcc Physical Connections Pin Plcc Pin LayoutPackage Markings 28-pin Plcc Diagram below illustrates a simple +3.3V voltage sourcePin Tqfp AXC Pin Layout Pin Tqfp Physical ConnectionsPower for USB Transceivers . V DD1 may be connected to V DD 48/28-Pin USB Host Controller Pins DescriptionData 6. Microprocessor Data/Address Bus Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 7. Microprocessor Data/Address Bus Buffer or registerPackage Markings 48-Pin Tqfp Yyww XxxxElectrical Specifications DC Characteristics Parameter Description Min Typ Max Write Cycle Bus Interface Timing RequirementsParameter Description Min Typ Max NWR HighRead Cycle DMA Write Cycle DMA Write CycleDMA Read Cycle Reset TimingNRst Pulse width NRst High to nRD or nWR activeOrdering Information Package DiagramsCLOCKClock TimingTIMING Parameter Description Min Typ Max Part Number Package TypeLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Document History Issue Date Orig. Description of ChangeREV ECN no
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