Cypress manual SL811HS Registers, MHz Crystals, Frequency Tolerance, USB Transceiver

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SL811HS

PLL Clock Generator

Typical Crystal Requirements

Either a 12 MHz or a 48 MHz external crystal is used with the SL811HS[1]. Two pins, X1 and X2, are provided to connect a low cost crystal circuit to the device as shown in Figure 2 and Figure 3. Use an external clock source if available in the appli- cation instead of the crystal circuit by connecting the source directly to the X1 input pin. When a clock is used, the X2 pin is not connected.

When the CM pin is tied to a logic 0, the internal PLL is bypassed so the clock source must meet the timing require- ments specified by the USB specification.

Figure 2. Full Speed 48 MHz Crystal Circuit

X1

X2

Rf

 

1M

 

 

Rs

X1

100

48 MHz, series, 20-pF load

 

Cbk

 

0.01 μF

 

 

Lin

Cout

Cin

22 pF

2.2

22 pF

μH

 

 

The following are examples of ‘typical requirements.’ Note that these specifications are generally found as standard crystal values and are less expensive than custom values. If crystals are used in series circuits, load capacitance is not applicable. Load capacitance of parallel circuits is a requirement. 48 MHz third overtone crystals require the Cin/Lin filter to guarantee 48 MHz operation.

12 MHz Crystals:

 

Frequency Tolerance:

±100 ppm or better

Operating Temperature Range:

0°C to 70°C

Frequency:

12 MHz

Frequency Drift over Temperature:

± 50 ppm

ESR (Series Resistance):

60Ω

Load Capacitance:

10 pF min.

Shunt Capacitance:

7 pF max.

Drive Level:

0.1–0.5 mW

Operating Mode:

fundamental

48 MHz Crystals:

 

Frequency Tolerance:

±100 ppm or better

Operating Temperature Range:

0°C to 70°C

Frequency:

48 MHz

Frequency Drift over Temperature:

± 50 ppm

ESR (Series Resistance):

40 Ω

Load Capacitance:

10 pF min.

Shunt Capacitance:

7 pF max.

Drive Level:

0.1–0.5 mW

Operating Mode:

third overtone

 

Figure 3. Optional 12 MHz Crystal Circuit

 

 

 

 

 

 

 

 

 

X1

 

 

 

 

 

 

 

X2

 

 

 

 

 

Rf

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1M

 

 

 

 

 

 

 

 

 

Rs

 

 

100

 

 

 

 

 

X1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12 MHz , series, 20-pF load

 

Cin

 

 

 

 

 

 

 

Cout

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

22 pF

 

 

 

 

 

 

 

22 pF

 

 

 

 

 

 

 

Note

USB Transceiver

The SL811HS has a built in transceiver that meets USB Speci- fication 1.1. The transceiver is capable of transmitting and receiving serial data at USB full speed (12 Mbits) and low speed (1.5 Mbits). The driver portion of the transceiver is differ- ential while the receiver section is comprised of a differential receiver and two single-ended receivers. Internally, the trans- ceiver interfaces to the Serial Interface Engine (SIE) logic. Externally, the transceiver connects to the physical layer of the USB.

SL811HS Registers

Operation and control of the SL811HS is managed through internal registers. When operating in Master/Host mode, the first 16 address locations are defined as register space. In Slave/Peripheral mode, the first 64 bytes are defined as register space. The register definitions vary greatly between each mode of operation and are defined separately in this document (section “SL811HS Master (Host) Mode Registers” on page 4 describes Host register definitions, while section

1. CM (Clock Multiply) pin of the SL811HS must be tied to GND when 48 MHz crystal circuit or 48 MHz clock source is used.

Document 38-08008 Rev. *D

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Contents Cypress Semiconductor Corporation FeaturesIntroduction Master/Slave ControllerInterrupt Controller DMA Controller slave mode onlyAuto Address Increment Mode Data Port, Microprocessor InterfaceUSB Transceiver SL811HS RegistersMHz Crystals Frequency ToleranceRegister Values on Power Up and Reset USB Control RegistersSL811HS Host Control Registers ISO Bit Position Bit Name FunctionHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 D7-D4 HBL7 HBL6HBL4 HBL3 HBL2 HBL1 HBL0 PID TypeDA7 HTC7HTC2 DA6 DA5 DA4 DA3 DA2 DA1 DA0Control Register 1 Address 05h Bits 3 Low-power Modes Bit 6 Control Register, Address 05hUSB Reset Sequence Control Register 1 Address 05h BitUSB-B Done Interrupt Enable Register Address 06hUSB-B USB-A DoneRevision Reserved Bit Position Bit Name Function Interrupt Status Register Address 0Dh BitValue of the Data+ pin USB-BSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoints 0-3 Register Addresses Register Name Miscellaneous register addressesEndpoint Registers Endpoints 0-3 Register AddressesEPxLEN1 EPxLEN0 Endpoint Control RegistersSequence Next Data SetControl Register 0Fh SOF Low Byte Register Reserved OverflowTransmission Acknowledge Current Data Set RegisterControl Register 1 Address 05h Stbyd SpselStbyd Interrupt Status Register Address 0Dh USB Address Register, Address 07h. This registerUSB Address Register Address 07h USBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0SL811HS Current Data Set Register Address 0EhControl Register 2 Address 0Fh Bit Reserved Master/SlavePin Plcc Pin Layout Pin Plcc Mechanical DimensionsPhysical Connections Pin Plcc Physical ConnectionsPackage Markings 28-pin Plcc Diagram below illustrates a simple +3.3V voltage sourcePin Tqfp AXC Pin Layout Pin Tqfp Physical ConnectionsPower for USB Transceivers . V DD1 may be connected to V DD 48/28-Pin USB Host Controller Pins DescriptionBuffer or register Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 6. Microprocessor Data/Address Bus Data 7. Microprocessor Data/Address BusPackage Markings 48-Pin Tqfp Yyww XxxxElectrical Specifications DC Characteristics Parameter Description Min Typ Max NWR High Bus Interface Timing RequirementsWrite Cycle Parameter Description Min Typ MaxRead Cycle DMA Write Cycle DMA Write CycleNRst High to nRD or nWR active Reset TimingDMA Read Cycle NRst Pulse widthPart Number Package Type Package DiagramsOrdering Information CLOCKClock TimingTIMING Parameter Description Min Typ MaxLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Issue Date Orig. Description of Change Document HistoryREV ECN no