Cypress SL811HS Interrupt Enable Register Address 06h, Usb-B Usb-A, USB-B Done, USB-A Done

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SL811HS

Interrupt Enable Register [Address = 06h]. The SL811HS provides an Interrupt Request Output, which is activated for a number of conditions. The Interrupt Enable register allows the user to select conditions that result in an interrupt that is issued to an external CPU through the INTRQ pin. A separate Interrupt Status register reflects the reason for the interrupt. Enabling or disabling these interrupts does not have an effect on whether or not the corresponding bit in the Interrupt Status register is set or cleared; it only determines if the interrupt is

Table 13. Interrupt Enable Register [Address 06h]

routed to the INTRQ pin. The Interrupt Status register is normally used in conjunction with the Interrupt Enable register and can be polled in order to determine the conditions that initiated the interrupt (See the description for the Interrupt Status Register). When a bit is set to ’1’ the corresponding interrupt is enabled. So when the enabled interrupt occurs, the INTRQ pin is asserted. The INTRQ pin is a level interrupt, meaning it is not deasserted until all enabled interrupts are cleared.

Bit 7

Bit 6

 

Bit 5

Bit 4

Bit 3

 

Bit 2

Bit 1

Bit 0

Reserved

Device

 

Inserted/

SOF Timer

Reserved

 

Reserved

USB-B

USB-A

 

 

Detect/Resume

 

Removed

 

 

 

 

DONE

DONE

 

 

 

 

 

 

 

 

 

 

Bit Position

 

Bit Name

 

Function

 

 

 

 

 

7

 

Reserved

 

‘0’

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

Device Detect/Resume

Enable Device Detect/Resume Interrupt.

 

 

 

 

 

 

 

 

When bit 6 of register 05h (Control Register 1) is equal to ’1’, bit 6 of this register enables

 

 

 

 

 

the Resume Detect Interrupt. Otherwise, this bit is used to enable Device Detection

 

 

 

 

 

status as defined in the Interrupt Status register bit definitions.

 

5

 

Inserted/Removed

 

Enable Slave Insert/Remove Detection is used to enable/disable the device

 

 

 

 

 

inserted/removed interrupt.

 

 

 

4

 

SOF Timer

 

1 = Enable Interrupt for SOF Timer. This is typically at 1 mS intervals, although the

 

 

 

 

 

timing is determined by the SOF Counter high/low registers.

 

 

 

 

 

 

To use this bit function, bit 0 of register 05h must be enabled and the SOF counter

 

 

 

 

 

registers 0E hand 0Fh must be initialized.

 

 

 

3

 

Reserved

 

‘0’

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

Reserved

 

‘0’

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

USB-B DONE

 

USB-B Done Interrupt (see USB-A Done interrupt).

 

 

0

 

USB-A DONE

 

USB-A Done Interrupt. The Done interrupt is triggered by one of the events that are

 

 

 

 

 

logged in the USB Packet Status register. The Done interrupt causes the Packet Status

 

 

 

 

 

register to update.

 

 

 

 

 

USB Address Register, Reserved, Address [Address = 07h]. This register is reserved for the device USB Address in Slave operation. It should not be written by the user in host mode.

Registers 08h-0ChHost-B registers. Registers 08h-0Ch have the same definition as registers 00h-04h except they apply to Host-B instead of Host-A.

Document 38-08008 Rev. *D

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Contents Introduction FeaturesMaster/Slave Controller Cypress Semiconductor CorporationAuto Address Increment Mode DMA Controller slave mode onlyData Port, Microprocessor Interface Interrupt ControllerMHz Crystals SL811HS RegistersFrequency Tolerance USB TransceiverRegister Values on Power Up and Reset USB Control RegistersSL811HS Host Control Registers ISO Bit Position Bit Name FunctionHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 HBL4 HBL3 HBL2 HBL1 HBL0 HBL7 HBL6PID Type D7-D4HTC2 HTC7DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7USB Reset Sequence Low-power Modes Bit 6 Control Register, Address 05hControl Register 1 Address 05h Bit Control Register 1 Address 05h Bits 3USB-B USB-A Interrupt Enable Register Address 06hDone USB-B DoneValue of the Data+ pin Interrupt Status Register Address 0Dh BitUSB-B Revision Reserved Bit Position Bit Name FunctionSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoint Registers Register Name Miscellaneous register addressesEndpoints 0-3 Register Addresses Endpoints 0-3 Register AddressesSequence Endpoint Control RegistersNext Data Set EPxLEN1 EPxLEN0Transmission Acknowledge Reserved OverflowCurrent Data Set Register Control Register 0Fh SOF Low Byte RegisterControl Register 1 Address 05h Stbyd SpselStbyd USB Address Register Address 07h USB Address Register, Address 07h. This registerUSBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 Interrupt Status Register Address 0DhControl Register 2 Address 0Fh Bit Current Data Set Register Address 0EhReserved Master/Slave SL811HSPhysical Connections Pin Plcc Mechanical DimensionsPin Plcc Physical Connections Pin Plcc Pin LayoutPackage Markings 28-pin Plcc Diagram below illustrates a simple +3.3V voltage sourcePin Tqfp AXC Pin Layout Pin Tqfp Physical ConnectionsPower for USB Transceivers . V DD1 may be connected to V DD 48/28-Pin USB Host Controller Pins DescriptionData 6. Microprocessor Data/Address Bus Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 7. Microprocessor Data/Address Bus Buffer or registerPackage Markings 48-Pin Tqfp Yyww XxxxElectrical Specifications DC Characteristics Parameter Description Min Typ Max Write Cycle Bus Interface Timing RequirementsParameter Description Min Typ Max NWR HighRead Cycle DMA Write Cycle DMA Write CycleDMA Read Cycle Reset TimingNRst Pulse width NRst High to nRD or nWR activeOrdering Information Package DiagramsCLOCKClock TimingTIMING Parameter Description Min Typ Max Part Number Package TypeLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Issue Date Orig. Description of Change Document HistoryREV ECN no
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