Cypress SL811HS manual Control Register 1 Address 05h Bits 3, USB Reset Sequence

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SL811HS

Control Register 1 [Address = 05h]. The Control Register 1 enables/disables USB transfer operation with control bits defined as follows.

Table 11. Control Register 1 [Address 05h]

Bit 7

Bit 6

 

Bit 5

 

Bit 4

Bit 3

 

Bit 2

Bit 1

Bit 0

Reserved

Suspend

USB Speed

 

J-K state force

USB Engine

 

Reserved

Reserved

SOF ena/dis

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit Position

Bit Name

 

Function

 

 

 

 

 

 

7

Reserved

 

‘0’

 

 

 

 

 

 

6

Suspend

 

’1’ = enable, ’0’ = disable.

 

 

 

 

 

5

USB Speed

 

’0’ setup for full speed, ’1’ setup low speed.

 

 

 

4

J-K state force

 

See Table 12.

 

 

 

 

 

3

USB Engine Reset

USB Engine reset = ’1’. Normal set ’0’.

 

 

 

 

 

 

When a device is detected, the first thing that to do is to send it a USB Reset to force it into

 

 

 

its default address of zero. The USB 2.0 specification states that for a root hub a device

 

 

 

must be reset for a minimum of 50 mS.

 

 

 

2

Reserved

 

Some existing firmware examples set bit 2, but it is not necessary.

 

1

Reserved

 

‘0’

 

 

 

 

 

 

0

SOF ena/dis

 

’1’ = enable auto Hardware SOF generation; ’0’ = disable.

 

 

 

 

 

In the SL811HS, bit 0 is used to enable hardware SOF autogeneration. The generation of

 

 

 

SOFs continues when set to ‘0’, but SOF tokens are not output to USB.

 

At powe -up this register is cleared to all zeros.

Low-power Modes [Bit 6 Control Register, Address 05h]

When bit 6 (Suspend) is set to ’1’, the power of the transmit transceiver is turned off, the internal RAM is in suspend mode, and the internal clocks are disabled.

Note Any activity on the USB bus (i.e., K-State, etc.) resumes normal operation. To resume normal operation from the CPU side, a Data Write cycle (i.e., A0 set HIGH for a Data Write cycle) is done. This is a special case and not a normal direct write where the address is first written and then the data. To resume normal operation from the CPU side, you must do a Data Write cycle only.

Low Speed/Full Speed Modes [Bit 5 Control Register 1, Address 05h]

The SL811HS is designed to communicate with either full- or low speed devices. At power up bit 5 is LOW, i.e., for full speed. There are two cases when communicating with a low speed device. When a low speed device is connected directly to the SL811HS, bit 5 of Register 05h is set to ’1’ and bit 6 of register 0Fh, Polarity Swap, is set to ’1’ in order to change the polarity of D+ and D–. When a low speed device is connected via a HUB to SL811HS, bit 5 of Register 05h is set to ’0’ and bit 6 of register 0Fh is set to ’0’ in order to keep the polarity of D+ and D– for full speed. In addition, make sure that bit 7 of USB-A/USB-B Host Control registers [00h, 08h] is set to ’1’ for preamble generation.

J-K Programming States [Bits 4 and 3 of Control Register 1, Address 05h]

The J-K force state control and USB Engine Reset bits are used to generate a USB reset condition. Forcing K-state is

Notes

2.Force K-State for low speed.

3.Force J-State for low speed.

used for Peripheral device remote wake up, resume, and other modes. These two bits are set to zero on power up.

Table 12. Control Register 1 Address 05h – Bits 3 and 4

Bit 4

Bit 3

Function

0

0

Normal operating mode

 

 

 

0

1

Force USB Reset, D+ and D– are set LOW (SE0)

 

 

 

1

0

Force J-State, D+ set HIGH, D– set LOW[2]

1

1

Force K-State, D– set HIGH, D+ set LOW[3]

USB Reset Sequence

After a device is detected, write 08h to the Control register (05h) to initiate the USB reset, then wait for the USB reset time (root hub should be 50 ms) and additionally some types of devices such as a Forced J-state. Lastly, set the Control register (05h) back to 0h. After the reset is complete, the auto-SOF generation is enabled.

SOF Packet Generation

The SL811HS automatically computes the frame number and CRC5 by hardware. No CRC or SOF generation is required by external firmware for the SL811HS, although it can be done by sending an SOF PID in the Host PID, Device Endpoint register.

To enable SOF generation, assuming host mode is configured:

1.Set up the SOF interval in registers 0x0F and 0x0E.

2.Enable the SOF hardware generation in this register by setting bit 0 = ‘1’.

3.Set the Arm bit in the USB-A Host Control register.

Document 38-08008 Rev. *D

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Contents Features IntroductionMaster/Slave Controller Cypress Semiconductor CorporationDMA Controller slave mode only Auto Address Increment ModeData Port, Microprocessor Interface Interrupt ControllerSL811HS Registers MHz CrystalsFrequency Tolerance USB TransceiverSL811HS Host Control Registers Register Values on Power Up and ResetUSB Control Registers HBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 ISOBit Position Bit Name Function HBL7 HBL6 HBL4 HBL3 HBL2 HBL1 HBL0PID Type D7-D4HTC7 HTC2DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7Low-power Modes Bit 6 Control Register, Address 05h USB Reset SequenceControl Register 1 Address 05h Bit Control Register 1 Address 05h Bits 3Interrupt Enable Register Address 06h USB-B USB-ADone USB-B DoneInterrupt Status Register Address 0Dh Bit Value of the Data+ pinUSB-B Revision Reserved Bit Position Bit Name FunctionSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Register Name Miscellaneous register addresses Endpoint RegistersEndpoints 0-3 Register Addresses Endpoints 0-3 Register AddressesEndpoint Control Registers SequenceNext Data Set EPxLEN1 EPxLEN0Reserved Overflow Transmission AcknowledgeCurrent Data Set Register Control Register 0Fh SOF Low Byte RegisterStbyd Control Register 1 Address 05hStbyd Spsel USB Address Register, Address 07h. This register USB Address Register Address 07hUSBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 Interrupt Status Register Address 0DhCurrent Data Set Register Address 0Eh Control Register 2 Address 0Fh BitReserved Master/Slave SL811HSPin Plcc Mechanical Dimensions Physical ConnectionsPin Plcc Physical Connections Pin Plcc Pin LayoutDiagram below illustrates a simple +3.3V voltage source Package Markings 28-pin PlccPin Tqfp Physical Connections Pin Tqfp AXC Pin Layout48/28-Pin USB Host Controller Pins Description Power for USB Transceivers . V DD1 may be connected to V DDMaster/Slave Mode Select. ’1’ selects Slave. ’0’ = Master Data 6. Microprocessor Data/Address BusData 7. Microprocessor Data/Address Bus Buffer or registerYyww Xxxx Package Markings 48-Pin TqfpElectrical Specifications DC Characteristics Parameter Description Min Typ Max Bus Interface Timing Requirements Write CycleParameter Description Min Typ Max NWR HighRead Cycle DMA Write Cycle DMA Write CycleReset Timing DMA Read CycleNRst Pulse width NRst High to nRD or nWR activePackage Diagrams Ordering InformationCLOCKClock TimingTIMING Parameter Description Min Typ Max Part Number Package TypeLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 REV ECN no Issue Date Orig. Description of ChangeDocument History
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