Cypress SL811HS manual Document History, REV ECN no, Issue Date Orig. Description of Change

Page 32

SL811HS

Document History Page

Document Title: SL811HS Embedded USB Host/Slave Controller

Document Number: 38-08008

REV.

ECN NO.

Issue Date

Orig. of

 

 

Description of Change

Change

 

 

 

 

 

 

 

 

 

 

 

 

 

**

110850

12/14/01

BHA

Converted to Cypress format from ScanLogic

 

 

 

 

 

*A

112687

03/22/02

MUL

1) Changed power supply voltage to 4.0V in section 7.1

 

 

 

 

2)

Changed value of twdsu in section 7.6.2

 

 

 

 

3)

Changed max. power supply voltage to 3.45 V in section 7.2

 

 

 

 

4)

Changed accuracy of adjustment in section 7.2

 

 

 

 

5)

Changed bits 0 and 1 to reserved in section 5.3.8

 

 

 

 

6)

Changed bit 2 to reserved in section 5.3.5 and 5.3.7

 

 

 

 

7)

Changed bit 2 to reserved in section 5.3.1

 

 

 

 

8)

Changed definition of bit 6 in section 5.3.5 & 5.3.7

 

 

 

 

9)

Added section 5.1, Register Values on Power Up and Reset

 

 

 

 

10)

Changed bit description notes in section 5.3.7

 

 

 

 

11) Changed note about series termination resistors in section 7.5

 

 

 

 

12)

Changed example in section 5.3.9

 

 

 

 

13)

Changed J-K Programming States table in section 5.3.2

 

 

 

 

14)

Added and removed comments for low-power modes in section 5.3.4

 

 

 

 

15)

Removed sections specific to slave operation and SL11H

 

 

 

 

16)

Removed duplicate tables

 

 

 

 

17)

General formatting changes to section headings

 

 

 

 

18)

Fixed all part number references

 

 

 

 

19)

Added comments to section 7.5 and new definitions to section 2.0

*B

381894

See ECN

VCS

Went from single column to 2-column format. Combined information from

 

 

 

 

SL811HS (38-08008) and SL811S/T (83-08009)

*C

464641

See ECN

ARI

Added lead free part numbers to new section Ordering Information and

 

 

 

 

corrected references made to these parts. Corrected grammar. Added

 

 

 

 

compliance statement in section USB Host Transceiver Characteristics.

*D

749518

See ECN

ARI

Implemented the new template. Changed Figure 4. Labels on pins 2 and 3

 

 

 

 

were swapped; this has been corrected.

 

 

 

 

Combined the 48-pin TQFP AXC Pin Assignment and Definition table with

 

 

 

 

the 28-pin PLCC Pin Assignment and Definition table. Removed all instances

 

 

 

 

of SL811HST-AC. Corrected the variables. Removed references to the

 

 

 

 

obsolete SL11H.

Document 38-08008 Rev. *D

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Contents Features IntroductionMaster/Slave Controller Cypress Semiconductor CorporationDMA Controller slave mode only Auto Address Increment ModeData Port, Microprocessor Interface Interrupt ControllerSL811HS Registers MHz CrystalsFrequency Tolerance USB TransceiverSL811HS Host Control Registers Register Values on Power Up and ResetUSB Control Registers HBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 ISOBit Position Bit Name Function HBL7 HBL6 HBL4 HBL3 HBL2 HBL1 HBL0PID Type D7-D4HTC7 HTC2DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7Low-power Modes Bit 6 Control Register, Address 05h USB Reset SequenceControl Register 1 Address 05h Bit Control Register 1 Address 05h Bits 3Interrupt Enable Register Address 06h USB-B USB-ADone USB-B DoneInterrupt Status Register Address 0Dh Bit Value of the Data+ pinUSB-B Revision Reserved Bit Position Bit Name FunctionSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Register Name Miscellaneous register addresses Endpoint RegistersEndpoints 0-3 Register Addresses Endpoints 0-3 Register AddressesEndpoint Control Registers SequenceNext Data Set EPxLEN1 EPxLEN0Reserved Overflow Transmission AcknowledgeCurrent Data Set Register Control Register 0Fh SOF Low Byte RegisterStbyd Control Register 1 Address 05hStbyd Spsel USB Address Register, Address 07h. This register USB Address Register Address 07hUSBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 Interrupt Status Register Address 0DhCurrent Data Set Register Address 0Eh Control Register 2 Address 0Fh BitReserved Master/Slave SL811HSPin Plcc Mechanical Dimensions Physical ConnectionsPin Plcc Physical Connections Pin Plcc Pin LayoutDiagram below illustrates a simple +3.3V voltage source Package Markings 28-pin PlccPin Tqfp Physical Connections Pin Tqfp AXC Pin Layout48/28-Pin USB Host Controller Pins Description Power for USB Transceivers . V DD1 may be connected to V DDMaster/Slave Mode Select. ’1’ selects Slave. ’0’ = Master Data 6. Microprocessor Data/Address BusData 7. Microprocessor Data/Address Bus Buffer or registerYyww Xxxx Package Markings 48-Pin TqfpElectrical Specifications DC Characteristics Parameter Description Min Typ Max Bus Interface Timing Requirements Write CycleParameter Description Min Typ Max NWR HighRead Cycle DMA Write Cycle DMA Write CycleReset Timing DMA Read CycleNRst Pulse width NRst High to nRD or nWR activePackage Diagrams Ordering InformationCLOCKClock TimingTIMING Parameter Description Min Typ Max Part Number Package TypeLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 REV ECN no Issue Date Orig. Description of ChangeDocument History
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