Cypress SL811HS manual DC Characteristics Parameter Description Min Typ Max

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SL811HS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DC Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

Description

Min.

Typ.

Max.

 

VIL

Input Voltage LOW

–0.3V

 

0.8V

 

VIH

Input Voltage HIGH (5V Tolerant I/O)

2.0V

 

6.0V

 

VOL

Output Voltage LOW (IOL = 4 mA)

 

 

0.4V

 

VOH

Output Voltage HIGH (IOH = –4 mA)

2.4V

 

 

 

IOH

Output Current HIGH

4 mA

 

 

 

IOL

Output Current LOW

4 mA

 

 

 

ILL

Input Leakage

 

 

±1 μA

 

CIN

Input Capacitance

 

 

10 pF

 

ICC[13]

Supply Current (VDD) inc USB @FS

 

21 mA

25 mA

 

ICCsus1[14]

Supply Current (VDD) Suspend w/Clk & Pll Enb

 

4.2 mA

5 mA

 

ICCsus2[15]

Supply Current (VDD) Suspend no Clk & Pll Dis

 

50 μA

60 μA

 

IUSB

Supply Current (VDD1)

 

 

10 mA

 

IUSBSUS

Transceiver Supply Current in Suspend

 

 

10 μA

 

USB Host Transceiver Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

Description

 

Min.

Typ.[16]

Max.

 

VIHYS

Differential

 

0.2V

 

200 mV

 

 

Input Sensitivity (Data+, Data–)

 

 

 

 

 

VUSBIH

USB Input Voltage HIGH Driven

 

2.0V

 

 

 

VUSBIL

USB Input Voltage LOW

 

0.8V

 

 

 

VUSBOH

USB Output Voltage HIGH

 

2.0V

 

 

 

VUSBOL

USB Output Voltage LOW

 

0.0V

 

0.3V

 

ZUSBH[17]

Output Impedance HIGH STATE

 

36 Ohms

 

42 Ohms

 

ZUSBL[17]

Output Impedance LOW STATE

 

36 Ohms

 

42 Ohms

 

IUSB

Transceiver Supply p-p Current (3.3V)

 

 

 

10 mA

 

 

 

 

 

 

 

 

@ FS

 

Every VDD pin, including USB VDD, must have a decoupling capacitor to ensure clean VDD (free of high frequency noise) at the chip input point (pin) itself.

The best way to do this is to connect a ceramic capacitor (0.1 μF, 6V) between the pin itself and a good ground. Keep capacitor leads as short as possible. Use surface mount

capacitors with the shortest traces possible (the use of a ground plane is strongly recommended).

This product was tested as compliant to the USB-IF specifi- cation under the test identification number (TID) of 40000689 and is listed on the USB-IF’s integrators list.

Notes

13.ICC measurement includes USB Transceiver current (IUSB) operating at full speed.

14.ICCsus1 measured with 12 MHz Clock Input and Internal PLL enabled. Suspend set –(USB transceiver and internal Clocking disabled).

15.ICCsus2 measured with external Clock, PLL disabled, and Suspend set. For absolute minimum current consumption, ensure that all inputs to the device are at static logic level.

16.All typical values are VDD = 3.3V and TAMB= 25°C.

17.ZUSBX impedance values includes an external resistor of 24 Ohms ± 1% (SL811HS revision 1.2 requires external resistor values of 33 Ohms ±1%).

Document 38-08008 Rev. *D

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Contents Introduction FeaturesMaster/Slave Controller Cypress Semiconductor CorporationAuto Address Increment Mode DMA Controller slave mode onlyData Port, Microprocessor Interface Interrupt ControllerMHz Crystals SL811HS RegistersFrequency Tolerance USB TransceiverUSB Control Registers Register Values on Power Up and ResetSL811HS Host Control Registers Bit Position Bit Name Function ISOHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 HBL4 HBL3 HBL2 HBL1 HBL0 HBL7 HBL6PID Type D7-D4HTC2 HTC7DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7USB Reset Sequence Low-power Modes Bit 6 Control Register, Address 05hControl Register 1 Address 05h Bit Control Register 1 Address 05h Bits 3USB-B USB-A Interrupt Enable Register Address 06hDone USB-B DoneValue of the Data+ pin Interrupt Status Register Address 0Dh BitUSB-B Revision Reserved Bit Position Bit Name FunctionSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoint Registers Register Name Miscellaneous register addressesEndpoints 0-3 Register Addresses Endpoints 0-3 Register AddressesSequence Endpoint Control RegistersNext Data Set EPxLEN1 EPxLEN0Transmission Acknowledge Reserved OverflowCurrent Data Set Register Control Register 0Fh SOF Low Byte RegisterStbyd Spsel Control Register 1 Address 05hStbyd USB Address Register Address 07h USB Address Register, Address 07h. This registerUSBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 Interrupt Status Register Address 0DhControl Register 2 Address 0Fh Bit Current Data Set Register Address 0EhReserved Master/Slave SL811HSPhysical Connections Pin Plcc Mechanical DimensionsPin Plcc Physical Connections Pin Plcc Pin LayoutPackage Markings 28-pin Plcc Diagram below illustrates a simple +3.3V voltage sourcePin Tqfp AXC Pin Layout Pin Tqfp Physical ConnectionsPower for USB Transceivers . V DD1 may be connected to V DD 48/28-Pin USB Host Controller Pins DescriptionData 6. Microprocessor Data/Address Bus Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 7. Microprocessor Data/Address Bus Buffer or registerPackage Markings 48-Pin Tqfp Yyww XxxxElectrical Specifications DC Characteristics Parameter Description Min Typ Max Write Cycle Bus Interface Timing RequirementsParameter Description Min Typ Max NWR HighRead Cycle DMA Write Cycle DMA Write CycleDMA Read Cycle Reset TimingNRst Pulse width NRst High to nRD or nWR activeOrdering Information Package DiagramsCLOCKClock TimingTIMING Parameter Description Min Typ Max Part Number Package TypeLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Document History Issue Date Orig. Description of ChangeREV ECN no
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