Cypress SL811HS manual Read Cycle

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SL811HS

I/O Read Cycle

twr

nWR

twrrdl

twasu twahld

trdp

nRD

twdsu

D0-D7

nCS

twdhld

trcsu

tracc trdhld

DATA

trshld

Tcscs *Note

I/O Read Cycle from Register or Memory Buffer

Parameter	Description	Min.	Typ.	Max.

tWR	Write pulse width	85 ns
tRD	Read pulse width	85 ns
tWCSU	Chip select set-up to nWR	0 ns
tWASU	A0 address set-up time	85 ns
tWAHLD	A0 address hold time	10 ns
tWDSU	Data to Write HIGH set-up time	85 ns
tWDHLD	Data hold time after Write HIGH	5 ns
tRACC	Data valid after Read LOW	25 ns		85 ns
tRDHLD	Data hold after Read HIGH	40 ns
tRCSU	Chip select LOW to Read LOW	0 ns
tRSHLD	NCS hold after Read HIGH	0 ns
TCSCS*	nCS inactive to nCS *asserted	85 ns
tWRRDL	nWR HIGH to nRD LOW	85ns

Note nCS can be kept LOW during multiple Read cycles provided nRD is cycled. Rd Cycle Time for Auto Inc Mode Reads is 170 ns minimum.

Document 38-08008 Rev. *D

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Contents Cypress Semiconductor Corporation FeaturesIntroduction Master/Slave ControllerInterrupt Controller DMA Controller slave mode onlyAuto Address Increment Mode Data Port, Microprocessor InterfaceUSB Transceiver SL811HS RegistersMHz Crystals Frequency ToleranceRegister Values on Power Up and Reset USB Control RegistersSL811HS Host Control Registers ISO Bit Position Bit Name FunctionHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 D7-D4 HBL7 HBL6HBL4 HBL3 HBL2 HBL1 HBL0 PID TypeDA7 HTC7HTC2 DA6 DA5 DA4 DA3 DA2 DA1 DA0Control Register 1 Address 05h Bits 3 Low-power Modes Bit 6 Control Register, Address 05hUSB Reset Sequence Control Register 1 Address 05h BitUSB-B Done Interrupt Enable Register Address 06hUSB-B USB-A DoneRevision Reserved Bit Position Bit Name Function Interrupt Status Register Address 0Dh BitValue of the Data+ pin USB-BSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoints 0-3 Register Addresses Register Name Miscellaneous register addressesEndpoint Registers Endpoints 0-3 Register AddressesEPxLEN1 EPxLEN0 Endpoint Control RegistersSequence Next Data SetControl Register 0Fh SOF Low Byte Register Reserved OverflowTransmission Acknowledge Current Data Set RegisterControl Register 1 Address 05h Stbyd SpselStbyd Interrupt Status Register Address 0Dh USB Address Register, Address 07h. This registerUSB Address Register Address 07h USBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0SL811HS Current Data Set Register Address 0EhControl Register 2 Address 0Fh Bit Reserved Master/SlavePin Plcc Pin Layout Pin Plcc Mechanical DimensionsPhysical Connections Pin Plcc Physical ConnectionsPackage Markings 28-pin Plcc Diagram below illustrates a simple +3.3V voltage sourcePin Tqfp AXC Pin Layout Pin Tqfp Physical ConnectionsPower for USB Transceivers . V DD1 may be connected to V DD 48/28-Pin USB Host Controller Pins DescriptionBuffer or register Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 6. Microprocessor Data/Address Bus Data 7. Microprocessor Data/Address BusPackage Markings 48-Pin Tqfp Yyww XxxxElectrical Specifications DC Characteristics Parameter Description Min Typ Max NWR High Bus Interface Timing RequirementsWrite Cycle Parameter Description Min Typ MaxRead Cycle DMA Write Cycle DMA Write CycleNRst High to nRD or nWR active Reset TimingDMA Read Cycle NRst Pulse widthPart Number Package Type Package DiagramsOrdering Information CLOCKClock TimingTIMING Parameter Description Min Typ MaxLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Issue Date Orig. Description of Change Document HistoryREV ECN no