Cypress SL811HS Data 6. Microprocessor Data/Address Bus, Data 7. Microprocessor Data/Address Bus

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SL811HS

Table 35. 48/28-Pin TQFP AXC Pin Assignments and Definitions (continued)

	48-Pin TQFP	28-Pin PLCC	Pin Type	Pin Name	Pin Description
	AXC Pin No.	Pin No.	Pin Type	Pin Name	Pin Description
	AXC Pin No.	Pin No.
	33	25	BIDIR	D6	Data 6. Microprocessor Data/Address Bus.

	34	–	NC	NC	No connection.

	35	–	NC	NC	No connection.

	36	–	NC	NC	No connection.

	37	–	NC	NC	No connection.

	38	–	NC	NC	No connection.

	39	26	BIDIR	D7	Data 7. Microprocessor Data/Address Bus.

	40	27	IN	M/S	Master/Slave Mode Select. ’1’ selects Slave. ’0’ = Master.
	41	28[8]	VDD	+3.3 VDC	Device VDD Power.
	42[9]	1[9]	IN	A0	A0 = ’0’. Selects address pointer. Register A0 = ’1’. Selects data
					buffer or register.
	43	2	IN	nDACK	DMA Acknowledge. An active LOW input used to interface to
					an external DMA controller. DMA is enabled only in slave mode.
					In host mode, the pin should be tied HIGH (logic ’1’).
	44	3	OUT	nDRQ	DMA Request. An active LOW output used with an external
					DMA controller. nDRQ and nDACK form the handshake for DMA
					data transfers. In host mode, leave the pin unconnected.
	45	4	IN	nRD	Read Strobe Input. An active LOW input used with nCS to read
					registers/data memory.
	46	–	NC	NC	No connection.

	47	–	NC	NC	No connection.

	48	–	NC	NC	No connection.

Notes

8.VDD can be derived from the USB supply. Figure 5 on page 19 shows a simple method to provide 3.3V/30 mA. Another option is to use a Torex Semiconductor, Ltd. 3.3V SMD regulator (part number XC62HR3302MR).

9.The A0 Address bit is used to access address register or data registers in I/O Mapped or Memory Mapped applications.

Document 38-08008 Rev. *D

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Contents Master/Slave Controller FeaturesIntroduction Cypress Semiconductor CorporationData Port, Microprocessor Interface DMA Controller slave mode onlyAuto Address Increment Mode Interrupt ControllerFrequency Tolerance SL811HS RegistersMHz Crystals USB TransceiverUSB Control Registers Register Values on Power Up and ResetSL811HS Host Control Registers Bit Position Bit Name Function ISOHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 PID Type HBL7 HBL6HBL4 HBL3 HBL2 HBL1 HBL0 D7-D4DA6 DA5 DA4 DA3 DA2 DA1 DA0 HTC7HTC2 DA7Control Register 1 Address 05h Bit Low-power Modes Bit 6 Control Register, Address 05hUSB Reset Sequence Control Register 1 Address 05h Bits 3Done Interrupt Enable Register Address 06hUSB-B USB-A USB-B DoneUSB-B Interrupt Status Register Address 0Dh BitValue of the Data+ pin Revision Reserved Bit Position Bit Name FunctionSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoints 0-3 Register Addresses Register Name Miscellaneous register addressesEndpoint Registers Endpoints 0-3 Register AddressesNext Data Set Endpoint Control RegistersSequence EPxLEN1 EPxLEN0Current Data Set Register Reserved OverflowTransmission Acknowledge Control Register 0Fh SOF Low Byte RegisterStbyd Spsel Control Register 1 Address 05hStbyd USBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 USB Address Register, Address 07h. This registerUSB Address Register Address 07h Interrupt Status Register Address 0DhReserved Master/Slave Current Data Set Register Address 0EhControl Register 2 Address 0Fh Bit SL811HSPin Plcc Physical Connections Pin Plcc Mechanical DimensionsPhysical Connections Pin Plcc Pin LayoutDiagram below illustrates a simple +3.3V voltage source Package Markings 28-pin PlccPin Tqfp Physical Connections Pin Tqfp AXC Pin Layout48/28-Pin USB Host Controller Pins Description Power for USB Transceivers . V DD1 may be connected to V DDData 7. Microprocessor Data/Address Bus Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 6. Microprocessor Data/Address Bus Buffer or registerYyww Xxxx Package Markings 48-Pin TqfpElectrical Specifications DC Characteristics Parameter Description Min Typ Max Parameter Description Min Typ Max Bus Interface Timing RequirementsWrite Cycle NWR HighRead Cycle DMA Write Cycle DMA Write CycleNRst Pulse width Reset TimingDMA Read Cycle NRst High to nRD or nWR activeCLOCKClock TimingTIMING Parameter Description Min Typ Max Package DiagramsOrdering Information Part Number Package TypeLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Document History Issue Date Orig. Description of ChangeREV ECN no