Cypress SL811HS Bus Interface Timing Requirements, Write Cycle, Parameter Description Min Typ Max

SL811HS

Bus Interface Timing Requirements

I/O Write Cycle

twr

nWR

twrhigh

twasu twahld

	A0							twdsu
			twdsu			twdhld			twdhld
	D0-D7			Register or Memory				DATA
					Address
			twcsu		twshld
	nCS
							Tcscs See Note.
			I/O Write Cycle to Register or Memory Buffer
Parameter			Description			Min.		Typ.		Max.
tWR		Write pulse width				85 ns
tWCSU		Chip select set-up to nWR LOW				0 ns
tWSHLD		Chip select hold time				0 ns
		After nWR HIGH
tWASU		A0 address set-up time				85 ns
tWAHLD		A0 address hold time				10 ns
tWDSU		Data to Write HIGH set-up time				85 ns
tWDHLD		Data hold time after Write HIGH				5 ns
tCSCS		nCS inactive to nCS* asserted				85 ns
tWRHIGH		NWR HIGH				85 ns

Note nCS an be held LOW for multiple Write cycles provided nWR is cycled. Write Cycle Time for Auto Inc Mode Writes is 170 ns minimum.

Document 38-08008 Rev. *D Page 26 of 32