Cypress SL811HS Iso, Bit Position Bit Name Function, HBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0

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SL811HS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USB-A/USB-B Host Control Registers [Address = 00h, 08h] .

 

 

 

 

 

 

 

Table 3. USB-A/USB-B Host Control Register Definition [Address 00h, 08h]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit 7

Bit 6

 

Bit 5

Bit 4

 

Bit 3

 

Bit 2

 

Bit 1

Bit 0

Preamble

Data Toggle Bit

SyncSOF

ISO

 

Reserved

 

Direction

 

Enable

Arm

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit Position

 

Bit Name

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

Preamble

 

If bit = ’1’ a preamble token is transmitted before transfer of low speed packet. If bit = ’0’,

 

 

 

 

 

 

preamble generation is disabled.

 

 

 

 

 

 

 

 

 

 

 

• The SL811HS automatically generates preamble packets when bit 7 is set. This bit is only

 

 

 

 

 

 

used to send packets to a low speed device through a hub. To communicate to a full

 

 

 

 

 

 

speed device, this bit is set to ‘0’. For example, when SL811HS communicates to a low

 

 

 

 

 

 

speed device via the HUB:

 

 

 

 

 

 

 

 

 

 

 

 

 

— Set SL811HS SIE to operate at full speed, i.e., bit 5 of register 05h (Control Register 1)

 

 

 

 

 

 

= ’0’.

 

 

 

 

 

 

 

 

 

 

 

 

 

— Set

bit 6 of register 0Fh (Control Register 2) = ’0’. Set correct polarity of DATA+ and

 

 

 

 

 

 

DATA– state for full speed.

 

 

 

 

 

 

 

 

 

 

 

— Set

bit 7, Preamble bit, = ’1’ in the Host Control register.

 

 

 

 

 

 

 

 

 

• When SL811HS communicates directly to a low speed device:

 

 

 

 

 

 

 

 

— Set

bit 5 of register 05h (Control Register 1) = ’1’.

 

 

 

 

 

 

 

 

 

— Set bit 6 of register 0Fh (Control Register 2) = ’1’, DATA+ and DATA– polarity for low

 

 

 

 

 

 

speed.

 

 

 

 

 

 

 

 

 

 

 

 

 

— The state of bit 7 is ignored in this mode.

 

 

 

 

 

 

 

 

 

 

6

 

Data Toggle Bit

 

’0’ if DATA0, ’1’ if DATA1 (only used for OUT tokens in host mode).

 

 

 

 

 

 

 

 

 

5

 

SyncSOF

 

’1’ = Synchronize with the SOF transfer when operating in FS only.

 

 

 

 

 

 

 

 

The SL811HS uses bit 5 to enable transfer of a data packet after a SOF packet is transmitted.

 

 

 

 

 

 

When bit 5 = ‘1’, the next enabled packet is sent after next SOF. If bit 5 = ‘0’ the next packet

 

 

 

 

 

 

is sent immediately if the SIE is free. If operating in low speed, do not set this bit.

4

 

ISO

 

When set to ’1’, this bit allows Isochronous mode for this packet.

 

 

 

 

 

 

 

 

 

 

 

 

3

 

Reserved

 

Bit 3 is reserved for future use.

 

 

 

 

 

 

 

 

 

 

 

 

2

 

Direction

 

When equal to ’1’ transmit (OUT). When equal to ’0’ receive (IN).

 

 

 

 

 

 

 

1

 

Enable

 

If Enable = ’1’, this bit allows transfers to occur. If Enable = ’0’, USB transactions are ignored.

 

 

 

 

 

 

The Enable bit is used in conjunction with the Arm bit (bit 0 of this register) for USB transfers.

0

 

Arm

 

Allows enabled transfers when Arm = ’1’. Cleared to ’0’ when transfer is complete (when

 

 

 

 

 

 

Done Interrupt is asserted).

 

 

 

 

 

 

 

Once the other SL811HS Control registers are configured (registers 01h-04h or 09h-0Ch) the Host Control register is programmed to initiate the USB transfer. This register initiates the transfer when the Enable and Arm bit are set as described above.

USB-A/USB-B Host Base Address [Address = 01h, 09h] .

Table 4. USB-A/USB-B Host Base Address Definition [Address 01h, 09h]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

HBADD7

HBADD6

HBADD5

HBADD4

HBADD3

HBADD2

HBADD1

HBADD0

 

 

 

 

 

 

 

 

The USB-A/B Base Address is a pointer to the SL811HS memory buffer location for USB reads and writes. When transferring data OUT (Host to Device), the USB-A and USB-B Host Base Address registers can be set up before setting ARM on the USB-A or USB-B Host Control register. When using a double buffer scheme, the Host Base Address could be set up with the first buffer used for DATA0 data and the other for DATA1 data.

Document 38-08008 Rev. *D

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Contents Introduction FeaturesMaster/Slave Controller Cypress Semiconductor CorporationAuto Address Increment Mode DMA Controller slave mode onlyData Port, Microprocessor Interface Interrupt ControllerMHz Crystals SL811HS RegistersFrequency Tolerance USB TransceiverSL811HS Host Control Registers Register Values on Power Up and ResetUSB Control Registers HBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 ISOBit Position Bit Name Function HBL4 HBL3 HBL2 HBL1 HBL0 HBL7 HBL6PID Type D7-D4HTC2 HTC7DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7USB Reset Sequence Low-power Modes Bit 6 Control Register, Address 05hControl Register 1 Address 05h Bit Control Register 1 Address 05h Bits 3USB-B USB-A Interrupt Enable Register Address 06hDone USB-B DoneValue of the Data+ pin Interrupt Status Register Address 0Dh BitUSB-B Revision Reserved Bit Position Bit Name FunctionSOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoint Registers Register Name Miscellaneous register addressesEndpoints 0-3 Register Addresses Endpoints 0-3 Register AddressesSequence Endpoint Control RegistersNext Data Set EPxLEN1 EPxLEN0Transmission Acknowledge Reserved OverflowCurrent Data Set Register Control Register 0Fh SOF Low Byte RegisterStbyd Control Register 1 Address 05hStbyd Spsel USB Address Register Address 07h USB Address Register, Address 07h. This registerUSBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 Interrupt Status Register Address 0DhControl Register 2 Address 0Fh Bit Current Data Set Register Address 0EhReserved Master/Slave SL811HSPhysical Connections Pin Plcc Mechanical DimensionsPin Plcc Physical Connections Pin Plcc Pin LayoutPackage Markings 28-pin Plcc Diagram below illustrates a simple +3.3V voltage sourcePin Tqfp AXC Pin Layout Pin Tqfp Physical ConnectionsPower for USB Transceivers . V DD1 may be connected to V DD 48/28-Pin USB Host Controller Pins DescriptionData 6. Microprocessor Data/Address Bus Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 7. Microprocessor Data/Address Bus Buffer or registerPackage Markings 48-Pin Tqfp Yyww XxxxElectrical Specifications DC Characteristics Parameter Description Min Typ Max Write Cycle Bus Interface Timing RequirementsParameter Description Min Typ Max NWR HighRead Cycle DMA Write Cycle DMA Write CycleDMA Read Cycle Reset TimingNRst Pulse width NRst High to nRD or nWR activeOrdering Information Package DiagramsCLOCKClock TimingTIMING Parameter Description Min Typ Max Part Number Package TypeLead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 REV ECN no Issue Date Orig. Description of ChangeDocument History