Cypress CY7C1161V18, CY7C1165V18 manual Write Cycle Descriptions, Comments, Remains unaltered

Page 11

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1161V18, CY7C1176V18

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1163V18, CY7C1165V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle Descriptions

 

 

 

 

 

 

The write cycle descriptions of CY7C1161V18 and CY7C1163V18 follow.[3, 11]

 

 

 

 

BWS

0/

 

BWS

1/

K

 

 

 

 

 

 

Comments

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NWS0

 

NWS1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

L–H

 

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1161V18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1163V18 both bytes (D[17:0]) are written into the device.

 

 

 

 

L

 

L

 

L-H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1161V18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1163V18 both bytes (D[17:0]) are written into the device.

 

 

 

 

L

 

H

L–H

 

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1161V18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

CY7C1163V18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

L

 

H

 

L–H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1161V18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

CY7C1163V18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

H

 

L

L–H

 

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1161V18 only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

CY7C1163V18 only the upper byte (D[17:9]) is written into the device, D[8:0]

remains unaltered.

 

H

 

L

 

L–H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1161V18 only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

CY7C1163V18 only the upper byte (D[17:9]) is written into the device, D[8:0]

remains unaltered.

 

H

 

H

L–H

 

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

 

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

The write cycle operation of CY7C1176V18 follows.[3, 11]

 

 

 

 

BWS

0

 

K

K

 

 

 

 

 

Comments

 

 

 

 

L

 

L–H

 

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

 

L

 

L–H

 

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

 

H

 

L–H

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

L–H

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

11.Is based upon a Write cycle was portions of a Write cycle, as long

initiated per the Write Cycle Description Truth Table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different as the setup and hold requirements are achieved.

Document Number: 001-06582 Rev. *D

Page 11 of 29

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Contents Selection Guide FeaturesConfigurations Functional DescriptionDoff Logic Block Diagram CY7C1161V18Logic Block Diagram CY7C1176V18 Logic Block Diagram CY7C1165V18 Logic Block Diagram CY7C1163V18NC/144M Pin ConfigurationsCY7C1161V18 2M x CY7C1176V18 2M xWPS BWS RPS CY7C1163V18 1M xCY7C1165V18 512K x Negative Input Clock Input Pin DefinitionsPin Name Pin Description TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagByte Write Operations Functional OverviewRead Operations Write OperationsEcho Clocks Valid Data Indicator QvldDepth Expansion Programmable ImpedanceWrite Cycle Load Application ExampleTruth Table OperationDuring the data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredDevice. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1165V18 follows.3Device Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Tap Controller State Diagram12 TAP Controller State DiagramParameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP ControllerTAP Timing and Test Conditions TAP AC Switching CharacteristicsInstruction Codes Identification Register DefinitionsScan Register Sizes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II+ SRAPower Up Sequence Power Up WaveformsOperating Range Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsParameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and WaveformsLOW Switching CharacteristicsParameter Min Max HighDLL Lock Time K Clock Phase JitterStatic to DLL Reset Parameter Min Max DLL TimingRead Write NOP Ordering Information 333 Ball Fbga 13 x 15 x 1.4 mm Package DiagramVKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History NXR