Cypress CY7C1163V18 manual Logic Block Diagram CY7C1161V18, Logic Block Diagram CY7C1176V18, Doff

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CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

Logic Block Diagram (CY7C1161V18)

D[7:0]

Address

A(18:0)

CLK

Gen.

DOFF

VREF

WPS

Control

NWS

Logic

[1:0]

Write

Address

Reg

Decode

512K x

Decode

WriteAdd.

8Array

ReadAdd.

Logic

Control

Read Data Reg.

Reg.

19A(18:0)

RPS

Q[7:0]

QVLD

Logic Block Diagram (CY7C1176V18)

D[8:0]

Address

A(18:0)

CLK

Gen.

DOFF

VREF

WPS

Control

BWS

[0]

Logic

Write

Address

Reg

Decode

512K x

Decode

WriteAdd.

9Array

ReadAdd.

Logic

Control

Read Data Reg.

Reg.

19A(18:0)

RPS

Q[8:0]

QVLD

Document Number: 001-06582 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1161V18Logic Block Diagram CY7C1176V18 Logic Block Diagram CY7C1163V18 Logic Block Diagram CY7C1165V18CY7C1176V18 2M x Pin ConfigurationsCY7C1161V18 2M x NC/144MWPS BWS RPS CY7C1163V18 1M xCY7C1165V18 512K x Negative Input Clock Input Pin DefinitionsPin Name Pin Description TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagWrite Operations Functional OverviewRead Operations Byte Write OperationsProgrammable Impedance Valid Data Indicator QvldDepth Expansion Echo ClocksOperation Application ExampleTruth Table Write Cycle LoadRemains unaltered Write Cycle DescriptionsComments During the data portion of a write sequenceInto the device. D359 remains unaltered Write cycle descriptions of CY7C1165V18 follows.3Device Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram12TAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in QDR-II+ SRAPower Up Sequence DLL ConstraintsMaximum Ratings Electrical CharacteristicsAC Electrical Characteristics Operating RangeAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitHigh Switching CharacteristicsParameter Min Max LOWParameter Min Max DLL Timing Clock Phase JitterStatic to DLL Reset DLL Lock Time KRead Write NOP Ordering Information 333 Package Diagram Ball Fbga 13 x 15 x 1.4 mmNXR ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP