Cypress CY7C1163V18 manual Pin Definitions, Pin Name Pin Description, Negative Input Clock Input

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CY7C1161V18, CY7C1176V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1163V18, CY7C1165V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name

IO

 

 

 

 

Pin Description

 

 

D[x:0]

Input-

Data Input Signals. Sampled on the rising edge of K and

 

clocks during valid write operations.

 

K

 

 

 

 

 

 

 

 

 

 

Synchronous

CY7C1161V18−D[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1176V18−D[8:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1163V18−D[17:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1165V18−D[35:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active,

 

 

WPS

 

 

 

 

 

 

 

 

 

 

Synchronous

a write operation is initiated. Deasserting deselects the write port. Deselecting the write port causes

 

 

 

 

 

 

 

 

 

 

 

 

D[x:0] to be ignored.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0,

 

 

 

1,

Input-

Nibble Write Select 0, 1 − Active LOW (CY7C1161V18 Only). Sampled on the rising edge

of the

 

 

 

NWS

NWS

 

 

 

 

 

 

 

 

 

 

Synchronous

K and K clocks during Write operations. Used to select the nibble that is written into the device. NWS0

 

 

 

 

 

 

 

 

 

 

 

 

controls D[3:0] and NWS1 controls D[7:4].

 

 

 

 

 

 

 

 

 

 

 

 

All the nibble write selects are sampled on the same edge as the data. Deselecting a nibble write

 

 

 

 

 

 

 

 

 

 

 

 

select causes the corresponding nibble of data to be ignored and not written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0,

 

 

1,

Input-

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and

 

 

 

clocks

 

 

BWS

BWS

K

 

BWS2, BWS3

Synchronous

during write operations. Used to select the byte that is written into the device during the current portion

 

 

 

 

 

 

 

 

 

 

 

 

of the write operation. Bytes not written remain unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1176V18 − BWS0

controls D[8:0].

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1163V18 − BWS0

controls D[8:0] and

BWS

1 controls D[17:9]..

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1165V18 − BWS0

controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18], and BWS3

 

 

 

 

 

 

 

 

 

 

 

 

controls D[35:27].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

 

 

 

 

 

 

 

 

 

 

 

 

causes the corresponding byte of data to be ignored and not written into the device.

 

 

 

 

 

 

 

A

Input-

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.

 

 

 

 

 

 

 

 

 

 

 

Synchronous

These address inputs are multiplexed for both read and write operations. Internally, the device is

 

 

 

 

 

 

 

 

 

 

 

 

organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1161V18, 2M x 9 (4 arrays each of 512K

 

 

 

 

 

 

 

 

 

 

 

 

x 9) for CY7C1176V18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1163V18, and 512K x 36 (4

 

 

 

 

 

 

 

 

 

 

 

 

arrays each of 128K x 36) for CY7C1165V18. Therefore, only 19 address inputs are needed to access

 

 

 

 

 

 

 

 

 

 

 

 

the entire memory array of CY7C1161V18 and CY7C1176V18, 18 address inputs for CY7C1163V18,

 

 

 

 

 

 

 

 

 

 

 

 

and 17 address inputs for CY7C1165V18. These inputs are ignored when the appropriate port is

 

 

 

 

 

 

 

 

 

 

 

 

deselected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q[x:0]

Outputs-

Data Output Signals. These pins drive out the requested data during a read operation. Valid data

 

 

 

 

 

 

 

 

 

 

 

Synchronous

is driven out on the rising edge of both the K and K clocks during read operations or K and K when

 

 

 

 

 

 

 

 

 

 

 

 

in single clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1161V18 − Q[7:0].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1176V18 − Q[8:0].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1163V18 − Q[17:0].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1165V18 − Q[35:0].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active,

 

 

RPS

 

 

 

 

 

 

 

 

 

 

Synchronous

a read operation is initiated. Deasserting causes the read port to be deselected. When deselected,

 

 

 

 

 

 

 

 

 

 

 

 

the pending access is enabled to complete and the output drivers are automatically tri-stated following

 

 

 

 

 

 

 

 

 

 

 

 

the next rising edge of the K clock. Each read access consists of a burst of four sequential transfers.

 

 

 

 

 

 

 

 

 

QVLD

Valid Output

Valid Output Indicator. Indicates valid output data. QVLD is edge-aligned with CQ and

 

 

 

 

 

 

 

CQ.

 

 

 

 

 

 

 

 

 

 

Indicator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

Input-

Positive Input Clock Input. Rising edge of K is used to capture synchronous inputs to the device

 

 

 

 

 

 

 

 

 

 

 

Clock

and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising

 

 

 

 

 

 

 

 

 

 

 

 

edge of K.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Negative Input Clock Input.

 

is used to capture synchronous inputs presented to the device and

 

 

K

K

 

 

 

 

 

 

 

 

 

 

Clock

to drive out data through Q[x:0] when in single clock mode.

 

 

CQ

Echo Clock

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

 

 

 

 

 

 

 

 

 

 

 

 

clock (K) of the QDR-II+. The timings for the echo clocks are shown in “Switching Characteristics”

 

 

 

 

 

 

 

 

 

 

 

 

on page 23.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document Number: 001-06582 Rev. *D

 

 

 

 

 

 

 

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1161V18 Logic Block Diagram CY7C1176V18Doff Logic Block Diagram CY7C1163V18 Logic Block Diagram CY7C1165V18CY7C1176V18 2M x Pin ConfigurationsCY7C1161V18 2M x NC/144MCY7C1163V18 1M x CY7C1165V18 512K xWPS BWS RPS Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagWrite Operations Functional OverviewRead Operations Byte Write OperationsProgrammable Impedance Valid Data Indicator QvldDepth Expansion Echo ClocksOperation Application ExampleTruth Table Write Cycle LoadRemains unaltered Write Cycle DescriptionsComments During the data portion of a write sequenceInto the device. D359 remains unaltered Write cycle descriptions of CY7C1165V18 follows.3Device Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram12TAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in QDR-II+ SRAPower Up Sequence DLL ConstraintsMaximum Ratings Electrical CharacteristicsAC Electrical Characteristics Operating RangeAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitHigh Switching CharacteristicsParameter Min Max LOWParameter Min Max DLL Timing Clock Phase JitterStatic to DLL Reset DLL Lock Time KRead Write NOP Ordering Information 333 Package Diagram Ball Fbga 13 x 15 x 1.4 mmNXR ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP
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