Cypress CY7C1165V18, CY7C1176V18, CY7C1163V18 manual Package Diagram, Ball Fbga 13 x 15 x 1.4 mm

Page 28

CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

Package Diagram

Figure 7. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180

15.00±0.10

A

TOP VIEW

PIN 1 CORNER

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

15.00±0.10

A

BOTTOM VIEW

 

 

 

 

 

 

 

PIN 1 CORNER

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

 

 

Ø0.25 M C A B

 

 

 

 

 

 

 

Ø0.50

-0.06

(165X)

 

 

 

 

 

 

 

 

+0.14

 

 

 

11

10

9

8

7

6

5

4

3

2

1

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

B

1.00

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

F

14.00

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

J

 

 

 

 

 

 

 

 

 

 

K

7.00

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

M

 

 

 

 

 

 

 

 

 

 

N

P

R

1.00

5.00

10.00

0.25 C

 

B

0.53±0.05

 

0.36

C

 

13.00±0.10

 

 

1.40MAX.

 

 

 

 

 

0.15C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SEATING PLANE

0.35±0.06

B 13.00±0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC

51-85180-*A

Document Number: 001-06582 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1176V18 Logic Block Diagram CY7C1161V18Doff Logic Block Diagram CY7C1163V18 Logic Block Diagram CY7C1165V18Pin Configurations CY7C1161V18 2M xCY7C1176V18 2M x NC/144MCY7C1165V18 512K x CY7C1163V18 1M xWPS BWS RPS Pin Name Pin Description Pin DefinitionsNegative Input Clock Input Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Read OperationsWrite Operations Byte Write OperationsValid Data Indicator Qvld Depth ExpansionProgrammable Impedance Echo ClocksApplication Example Truth TableOperation Write Cycle LoadWrite Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle descriptions of CY7C1165V18 follows.3 DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram12TAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionsScan Register Sizes Identification Register DefinitionsInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II+ SRA Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics AC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Parameter Min MaxHigh LOWClock Phase Jitter Static to DLL ResetParameter Min Max DLL Timing DLL Lock Time KRead Write NOP Ordering Information 333 Package Diagram Ball Fbga 13 x 15 x 1.4 mmECN No Issue Date Orig. Description of Change Document HistoryNXR VKN/KKVTMP
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