Cypress CY7C1163V18, CY7C1165V18, CY7C1176V18, CY7C1161V18 manual Ordering Information

Page 26

CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

Ordering Information

Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
400	CY7C1161V18-400BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1176V18-400BZC

	CY7C1163V18-400BZC

	CY7C1165V18-400BZC

	CY7C1161V18-400BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1176V18-400BZXC

	CY7C1163V18-400BZXC

	CY7C1165V18-400BZXC

	CY7C1161V18-400BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1176V18-400BZI

	CY7C1163V18-400BZI

	CY7C1165V18-400BZI

	CY7C1161V18-400BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1176V18-400BZXI

	CY7C1163V18-400BZXI

	CY7C1165V18-400BZXI

375	CY7C1161V18-375BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1176V18-375BZC

	CY7C1163V18-375BZC

	CY7C1165V18-375BZC

	CY7C1161V18-375BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1176V18-375BZXC

	CY7C1163V18-375BZXC

	CY7C1165V18-375BZXC

	CY7C1161V18-375BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1176V18-375BZI

	CY7C1163V18-375BZI

	CY7C1165V18-375BZI

	CY7C1161V18-375BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1176V18-375BZXI

	CY7C1163V18-375BZXI

	CY7C1165V18-375BZXI

Document Number: 001-06582 Rev. *D

Page 26 of 29

[+] Feedback

Image 26

Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1161V18Logic Block Diagram CY7C1176V18 Logic Block Diagram CY7C1163V18 Logic Block Diagram CY7C1165V18CY7C1176V18 2M x Pin ConfigurationsCY7C1161V18 2M x NC/144MWPS BWS RPS CY7C1163V18 1M xCY7C1165V18 512K x Negative Input Clock Input Pin DefinitionsPin Name Pin Description TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagWrite Operations Functional OverviewRead Operations Byte Write OperationsProgrammable Impedance Valid Data Indicator QvldDepth Expansion Echo ClocksOperation Application ExampleTruth Table Write Cycle LoadRemains unaltered Write Cycle DescriptionsComments During the data portion of a write sequenceInto the device. D359 remains unaltered Write cycle descriptions of CY7C1165V18 follows.3Device Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram12TAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in QDR-II+ SRAPower Up Sequence DLL ConstraintsMaximum Ratings Electrical CharacteristicsAC Electrical Characteristics Operating RangeAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitHigh Switching CharacteristicsParameter Min Max LOWParameter Min Max DLL Timing Clock Phase JitterStatic to DLL Reset DLL Lock Time KRead Write NOP Ordering Information 333 Package Diagram Ball Fbga 13 x 15 x 1.4 mmNXR ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP