Cypress CY7C1161V18 manual TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag

Page 7

 

 

 

 

 

 

 

CY7C1161V18, CY7C1176V18

 

 

 

 

 

 

 

CY7C1163V18, CY7C1165V18

 

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

 

 

Pin Name

IO

 

 

Pin Description

 

 

 

 

Echo Clock

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

 

CQ

 

 

 

 

 

clock (K) of the QDR-II+. The timings for the echo clocks are shown in “Switching Characteristics”

 

 

 

 

 

on page 23.

 

 

 

 

 

ZQ

Input

Output Impedance Matching Input. Used to tune the device outputs to the system data bus

 

 

 

 

 

impedance. CQ, CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor

 

 

 

 

 

connected between ZQ and ground. Alternatively, this pin is connected directly to VDDQ, which

 

 

 

 

 

enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-

 

 

 

 

 

nected.

 

 

 

 

 

 

 

 

 

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The

 

DOFF

 

 

 

 

 

timings in the DLL turned-off operation are different from those listed in this data sheet. For normal

 

 

 

 

 

operation, this pin is connected to a pull up through a 10 KΩ or less pull up resistor. The device

 

 

 

 

 

behaves in QDR-I mode when the DLL is turned off. In this mode, the device operates at a frequency

 

 

 

 

 

of up to 167 MHz with QDR-I timing.

 

 

 

 

 

TDO

Output

TDO for JTAG.

 

 

 

 

 

TCK

Input

TCK Pin for JTAG.

 

 

 

 

 

TDI

Input

TDI Pin for JTAG.

 

 

 

 

 

TMS

Input

TMS Pin for JTAG.

 

 

 

 

 

NC

N/A

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

NC/36M

N/A

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

NC/72M

N/A

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

NC/144M

N/A

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

NC/288M

N/A

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

VREF

Input-

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and

 

 

 

 

Reference

AC measurement points.

 

VDD

Power Supply

Power Supply Inputs to the Core of the Device.

 

VSS

Ground

Ground for the Device.

 

VDDQ

Power Supply

Power Supply Inputs for the Outputs of the Device.

Document Number: 001-06582 Rev. *D

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1176V18 Logic Block Diagram CY7C1161V18Doff Logic Block Diagram CY7C1165V18 Logic Block Diagram CY7C1163V18NC/144M Pin ConfigurationsCY7C1161V18 2M x CY7C1176V18 2M xCY7C1165V18 512K x CY7C1163V18 1M xWPS BWS RPS Pin Name Pin Description Pin DefinitionsNegative Input Clock Input TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagByte Write Operations Functional OverviewRead Operations Write OperationsEcho Clocks Valid Data Indicator QvldDepth Expansion Programmable ImpedanceWrite Cycle Load Application ExampleTruth Table OperationDuring the data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredDevice. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1165V18 follows.3Device Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Tap Controller State Diagram12 TAP Controller State DiagramParameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP ControllerTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II+ SRAPower Up Sequence Power Up WaveformsOperating Range Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsParameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and WaveformsLOW Switching CharacteristicsParameter Min Max HighDLL Lock Time K Clock Phase JitterStatic to DLL Reset Parameter Min Max DLL TimingRead Write NOP Ordering Information 333 Ball Fbga 13 x 15 x 1.4 mm Package DiagramVKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History NXR
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