Cypress CY7C1176V18, CY7C1165V18 Maximum Ratings, Operating Range, Electrical Characteristics

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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested.

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with Power Applied. –55°C to + 125°C

Supply Voltage on VDD Relative to GND

–0.5V to + 2.9V

Supply Voltage on VDDQ Relative to GND

–0.5V to + VDD

DC Applied to Outputs in High Z

–0.5V to VDDQ + 0.3V

DC Input Voltage[14]

–0.5V to V + 0.3V

 

 

DD

Current into Outputs (LOW)

20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015)..

> 2001V

Latch up Current

> 200 mA

Operating Range

Range

Ambient

V

[18]

V

[18]

Temperature (T )

 

A

 

DD

 

DDQ

Commercial

0°C to +70°C

1.8

± 0.1V

1.4V to

 

 

 

 

 

VDD

Industrial

–40°C to +85°C

 

 

 

Electrical Characteristics

The DC Electrical Characteristics over the operating range follows.[15]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

1.7

1.8

1.9

V

VDDQ

IO Supply Voltage

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 19

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 20

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = 0.1 mA, Nominal Impedance

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

VREF + 0.1

 

VDDQ + 0.15

V

VIL

Input LOW Voltage

 

 

–0.15

 

VREF – 0.1

V

IX

Input Leakage Current

GND VI VDDQ

 

2

 

2

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

2

 

2

μA

VREF

Input Reference Voltage[21]

Typical Value = 0.75V

 

0.68

0.75

0.95

V

IDD [22]

VDD Operating Supply

VDD = Max, IOUT = 0 mA,

300 MHz

 

 

850

mA

 

 

f = fmax = 1/tCYC

 

 

 

 

 

 

 

333 MHz

 

 

920

mA

 

 

 

375 MHz

 

 

1020

mA

 

 

 

 

 

 

 

 

 

 

 

400 MHz

 

 

1080

mA

 

 

 

 

 

 

 

 

ISB1

Automatic Power Down

Max VDD,

300 MHz

 

 

250

mA

 

Current

Both Ports Deselected,

 

 

 

 

 

 

333 MHz

 

 

260

mA

 

 

VIN VIH or VIN VIL

 

 

 

 

 

 

 

 

 

 

 

375 MHz

 

 

290

mA

 

 

f = fmax = 1/tCYC,

 

 

 

 

Inputs Static

400 MHz

 

 

300

mA

 

 

 

 

 

 

 

 

AC Electrical Characteristics

Over the operating range follows.[21]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VIH

Input HIGH Voltage

 

VREF + 0.2

VDDQ + 0.24

V

VIL

Input LOW Voltage

 

–0.24

VREF – 0.2

V

Notes

18.Power up: Is based upon a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

19.Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

20.Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

21.VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.

22.The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-06582 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1161V18 Logic Block Diagram CY7C1176V18Doff Logic Block Diagram CY7C1165V18 Logic Block Diagram CY7C1163V18CY7C1161V18 2M x Pin ConfigurationsCY7C1176V18 2M x NC/144MCY7C1163V18 1M x CY7C1165V18 512K xWPS BWS RPS Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsDepth Expansion Valid Data Indicator QvldProgrammable Impedance Echo ClocksTruth Table Application ExampleOperation Write Cycle LoadComments Write Cycle DescriptionsRemains unaltered During the data portion of a write sequenceDevice Write cycle descriptions of CY7C1165V18 follows.3Into the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Tap Controller State Diagram12 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Controller Parameter Description Test Conditions Min Max UnitTAP Timing and Test Conditions TAP AC Switching CharacteristicsIdentification Register Definitions Scan Register SizesInstruction Codes Bit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in QDR-II+ SRAPower Up Waveforms DLL ConstraintsAC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsHigh LOWStatic to DLL Reset Clock Phase JitterParameter Min Max DLL Timing DLL Lock Time KRead Write NOP Ordering Information 333 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History ECN No Issue Date Orig. Description of ChangeNXR VKN/KKVTMP