Cypress CY7C1165V18 manual Power Up Sequence in QDR-II+ SRA, DLL Constraints, Power Up Waveforms

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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18

Power Up Sequence in QDR-II+ SRA

During power up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock. QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

Power Up Sequence

■Apply power with DOFF tied HIGH (All other inputs can be HIGH or LOW)

❐Apply VDD before VDDQ

❐Apply VDDQ before VREF or at the same time as VREF

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var

■The DLL functions at frequencies down to 120 MHz

■If the input clock is unstable and the DLL is enabled, then the DLL locks onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency

■Provide stable power and clock (K, K) for 2048 cycles to lock the DLL

Power Up Waveforms

Figure 4. Power Up Waveforms

K

K

VDD/VDDQ

DOFF

~ ~

	~ ~

Unstable Clock	> 2048 Stable Clock	Start Normal
Clock Start (Clock Starts after VDD/VDDQ is Stable)		Operation
Clock Start (Clock Starts after VDD/VDDQ is Stable)

VDD/VDDQ Stable (< + 0.1V DC per 50 ns)

Fix HIGH (tie to VDDQ)

Document Number: 001-06582 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideDoff Logic Block Diagram CY7C1161V18Logic Block Diagram CY7C1176V18 Logic Block Diagram CY7C1163V18 Logic Block Diagram CY7C1165V18Pin Configurations CY7C1161V18 2M xCY7C1176V18 2M x NC/144MWPS BWS RPS CY7C1163V18 1M xCY7C1165V18 512K x Negative Input Clock Input Pin DefinitionsPin Name Pin Description Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Read OperationsWrite Operations Byte Write OperationsValid Data Indicator Qvld Depth ExpansionProgrammable Impedance Echo ClocksApplication Example Truth TableOperation Write Cycle LoadWrite Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle descriptions of CY7C1165V18 follows.3 DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram12TAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II+ SRA Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics AC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Parameter Min MaxHigh LOWClock Phase Jitter Static to DLL ResetParameter Min Max DLL Timing DLL Lock Time KRead Write NOP Ordering Information 333 Package Diagram Ball Fbga 13 x 15 x 1.4 mmECN No Issue Date Orig. Description of Change Document HistoryNXR VKN/KKVTMP