Cypress CY7C1163V18, CY7C1165V18 Capacitance, Thermal Resistance, AC Test Loads and Waveforms

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CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

Max

Unit

CIN

Input Capacitance

TA = 25°C, f = 1 MHz,

5

pF

 

 

VDD = 1.8V

 

 

CCLK

Clock Input Capacitance

6

pF

 

 

VDDQ = 1.5V

 

 

CO

Output Capacitance

7

pF

 

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

165 FBGA

Unit

Package

 

 

 

 

ΘJA

Thermal Resistance

Test conditions follow standard test methods and

17.2

°C/W

 

(junction to ambient)

procedures for measuring thermal impedance, in

 

 

 

 

accordance with EIA/JESD51.

 

 

ΘJC

Thermal Resistance

4.15

°C/W

 

 

(junction to case)

 

 

 

AC Test Loads and Waveforms

Figure 5. AC Test Loads and Waveforms

VREF = 0.75V

VREF

 

 

 

 

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

Z0 = 50Ω

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

Under

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

 

 

 

 

 

 

 

 

 

 

ZQ

RQ =

250Ω

(a)

RL = 50Ω

VREF = 0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF

 

 

 

 

 

 

0.75V

 

 

 

 

 

R = 50Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALL INPUT PULSES[23]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF 0.25V

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Under

ZQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slew Rate = 2 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

 

 

 

RQ =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

250Ω

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCOPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

23.Unless otherwise noted, test conditions are based upon signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.

Document Number: 001-06582 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1176V18 Logic Block Diagram CY7C1161V18Doff Logic Block Diagram CY7C1163V18 Logic Block Diagram CY7C1165V18CY7C1176V18 2M x Pin ConfigurationsCY7C1161V18 2M x NC/144MCY7C1165V18 512K x CY7C1163V18 1M xWPS BWS RPS Pin Name Pin Description Pin DefinitionsNegative Input Clock Input TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagWrite Operations Functional OverviewRead Operations Byte Write OperationsProgrammable Impedance Valid Data Indicator QvldDepth Expansion Echo ClocksOperation Application ExampleTruth Table Write Cycle LoadRemains unaltered Write Cycle DescriptionsComments During the data portion of a write sequenceInto the device. D359 remains unaltered Write cycle descriptions of CY7C1165V18 follows.3Device Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram12TAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionsScan Register Sizes Identification Register DefinitionsInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in QDR-II+ SRAPower Up Sequence DLL ConstraintsMaximum Ratings Electrical CharacteristicsAC Electrical Characteristics Operating RangeAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitHigh Switching CharacteristicsParameter Min Max LOWParameter Min Max DLL Timing Clock Phase JitterStatic to DLL Reset DLL Lock Time KRead Write NOP Ordering Information 333 Package Diagram Ball Fbga 13 x 15 x 1.4 mmNXR ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP