Cypress CY7C1163V18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

Identification Register Definitions

	Instruction Field		Value			Description
	Instruction Field	CY7C1161V18	CY7C1176V18	CY7C1163V18	CY7C1165V18	Description
		CY7C1161V18	CY7C1176V18	CY7C1163V18	CY7C1165V18
	Revision Number	000	000	000	000	Version number.
	(31:29)
	Cypress Device ID	11010010001000101	11010010001001101	11010010001010101	11010010001100101	Defines the type of
	(28:12)					SRAM.
	Cypress JEDEC ID	00000110100	00000110100	00000110100	00000110100	Enables unique
	(11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an ID
						register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	107

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input and output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI
		and TDO. This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input and output contents. Places the boundary scan register between
		TDI and TDO. This forces all SRAM output drivers to a High Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input and output ring contents. Places the boundary scan register
		between TDI and TDO. This operation does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect
		SRAM operation.

Document Number: 001-06582 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1161V18 Logic Block Diagram CY7C1176V18Doff Logic Block Diagram CY7C1163V18 Logic Block Diagram CY7C1165V18CY7C1176V18 2M x Pin ConfigurationsCY7C1161V18 2M x NC/144MCY7C1163V18 1M x CY7C1165V18 512K xWPS BWS RPS Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagWrite Operations Functional OverviewRead Operations Byte Write OperationsProgrammable Impedance Valid Data Indicator QvldDepth Expansion Echo ClocksOperation Application ExampleTruth Table Write Cycle LoadRemains unaltered Write Cycle DescriptionsComments During the data portion of a write sequenceInto the device. D359 remains unaltered Write cycle descriptions of CY7C1165V18 follows.3Device Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram12TAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in QDR-II+ SRAPower Up Sequence DLL ConstraintsMaximum Ratings Electrical CharacteristicsAC Electrical Characteristics Operating RangeAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitHigh Switching CharacteristicsParameter Min Max LOWParameter Min Max DLL Timing Clock Phase JitterStatic to DLL Reset DLL Lock Time KRead Write NOP Ordering Information 333 Package Diagram Ball Fbga 13 x 15 x 1.4 mmNXR ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP