Cypress CY7C1176V18, CY7C1165V18, CY7C1163V18 Depth Expansion, Programmable Impedance, Echo Clocks

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CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18

Depth Expansion

The CY7C1163V18 has a port select input for each port. This enables easy depth expansion. Both port selects are only sampled on the rising edge of the positive input clock (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the QDR-II+ to simplify data capture on high speed systems. Two echo clocks are generated by the QDR-II+. CQ is referenced with respect to K and CQ is refer- enced with respect to K. These are free running clocks and are synchronized to the input clock of the QDR-II+. The timings for the echo clocks are shown in the AC timing table.

Valid Data Indicator (QVLD)

QVLD is provided on the QDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the QDR-II+ device along with data output. This signal is also edge-aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives.

DLL

These chips utilize a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in QDR-I mode (with 1.0 cycle latency and a longer access time). For more information, refer to the application note, “DLL Consid- erations in QDRII/DDRII/QDRII+/DDRII+.” The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be reset in order to lock to the desired frequency. During power up when the DOFF is tied HIGH, the DLL is locked after 2048 cycles of stable clock.

Document Number: 001-06582 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1161V18 Logic Block Diagram CY7C1176V18Doff Logic Block Diagram CY7C1165V18 Logic Block Diagram CY7C1163V18CY7C1161V18 2M x Pin ConfigurationsCY7C1176V18 2M x NC/144MCY7C1163V18 1M x CY7C1165V18 512K xWPS BWS RPS Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsDepth Expansion Valid Data Indicator QvldProgrammable Impedance Echo ClocksTruth Table Application ExampleOperation Write Cycle LoadComments Write Cycle DescriptionsRemains unaltered During the data portion of a write sequenceDevice Write cycle descriptions of CY7C1165V18 follows.3Into the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Tap Controller State Diagram12 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Controller Parameter Description Test Conditions Min Max UnitTAP Timing and Test Conditions TAP AC Switching CharacteristicsIdentification Register Definitions Scan Register SizesInstruction Codes Bit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in QDR-II+ SRAPower Up Waveforms DLL ConstraintsAC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsHigh LOWStatic to DLL Reset Clock Phase JitterParameter Min Max DLL Timing DLL Lock Time KRead Write NOP Ordering Information 333 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History ECN No Issue Date Orig. Description of ChangeNXR VKN/KKVTMP
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