Cypress CY7C1256V18, CY7C1241V18 manual Write Cycle Descriptions, Comments, Remains unaltered

Page 11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1241V18, CY7C1256V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1243V18, CY7C1245V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle Descriptions

 

 

 

The write cycle description table for CY7C1241V18 and CY7C1243V18 follows.[2, 10]

 

 

 

 

BWS

0/

 

BWS

1/

K

 

 

 

 

 

 

Comments

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NWS0

 

NWS1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

L–H

 

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1241V18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1243V18 both bytes (D[17:0]) are written into the device.

 

 

 

 

L

 

L

 

L-H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1241V18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1243V18 both bytes (D[17:0]) are written into the device.

 

 

 

 

L

 

H

L–H

 

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1241V18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1243V18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

 

L

 

H

 

L–H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1241V18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1243V18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

 

H

 

L

L–H

 

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1241V18 only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1243V18 only the upper byte (D[17:9]) is written into the device, D[8:0]

remains unaltered.

 

 

H

 

L

 

L–H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1241V18 only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1243V18 only the upper byte (D[17:9]) is written into the device, D[8:0]

remains unaltered.

 

 

H

 

H

L–H

 

 

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

 

L–H

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle Descriptions

 

 

 

The write cycle description table for CY7C1256V18 follows.[2, 10]

 

 

 

 

BWS

0

 

K

 

K

 

 

 

 

 

 

Comments

 

 

 

 

L

 

L–H

 

 

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

 

 

 

L

 

L–H

 

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

 

 

 

H

 

L–H

 

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

L–H

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

10.Assumes a write cycle was initiated per the Write Cycle Description Table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered in different portions of a write cycle, as long as the setup and hold requirements are met.

Document Number: 001-06365 Rev. *D

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Contents Selection Guide FeaturesConfigurations Functional DescriptionDoff Logic Block Diagram CY7C1241V18Logic Block Diagram CY7C1256V18 Logic Block Diagram CY7C1245V18 Logic Block Diagram CY7C1243V18NC/144M Pin ConfigurationsCY7C1241V18 4M x CY7C1256V18 4M xWPS BWS RPS CY7C1243V18 2M xCY7C1245V18 1M x Negative Input Clock Input Pin DefinitionsPin Name Pin Description TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsProgrammable Impedance Valid Data Indicator QvldDelay Lock Loop DLL Depth ExpansionBUS Master Application ExampleTruth Table Sram #4During the data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredInto the device. D 80 and D 3518 remain unaltered Write cycle description table for CY7C1245V18 follows.2Into the device Written into the device. D 359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State DiagramParameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP ControllerTAP Timing and Test Conditions16 TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II+ SramPower Up Sequence Power Up WaveformsMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical CharacteristicsParameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and WaveformsSet-up Times Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxNOP Read Write Switching WaveformsOrdering Information Ball Fine Pitch Ball Grid Array 15 x 17 x 1.4 mm Lead-Free Ball Fbga 15 x 17 x 1.40 mm Package DiagramVKN/AESA Document HistoryNXR VKN/KKVTMP