Cypress CY7C1241V18, CY7C1243V18, CY7C1245V18, CY7C1256V18 manual Switching Waveforms, NOP Read Write

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CY7C1241V18, CY7C1256V18

CY7C1243V18, CY7C1245V18

Switching Waveforms

Figure 4. Read/Write/Deselect Sequence waveform for 2.0 Cycle Read Latency[30, 31, 32]

NOP	READ	WRITE	READ	WRITE	NOP
1	2	3	4	5	6	7	8

tKH

tKL tCYC tKHKH

RPS
tSC tHC	t SC tHC

WPS

QVLD

A0	A1	A2		A3
tSA tHA	t	HD		tSD		tHD
tSA tHA	t SD	HD		tSD
	t SD
		D10	D11	D12	D13	D30	D31	D32	D33
	tQVLD
			tCO		tDOH			tCQDOH
		tCLZ	tCO			tCQD		tCQDOH
		tCLZ				tCQD

tQVLD

tCHZ

Q00Q01Q02 Q03Q20 Q21 Q22Q23

(Read Latency = 2.0 Cycles)			t
		tCQOH	CCQO

tCQH tCQHCQH		t	CCQO
	tCQOH

DON’T CARE

UNDEFINED

Notes

30.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.

31.Outputs are disabled (High-Z) one clock cycle after a NOP.

32.In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-06365 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1241V18 Logic Block Diagram CY7C1256V18Doff Logic Block Diagram CY7C1243V18 Logic Block Diagram CY7C1245V18Pin Configurations CY7C1241V18 4M xCY7C1256V18 4M x NC/144MCY7C1243V18 2M x CY7C1245V18 1M xWPS BWS RPS Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Write OperationsByte Write Operations Read OperationsValid Data Indicator Qvld Delay Lock Loop DLLDepth Expansion Programmable ImpedanceApplication Example Truth TableSram #4 BUS MasterWrite Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle description table for CY7C1245V18 follows.2 Into the deviceWritten into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test Conditions16Identification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max Set-up TimesSwitching Waveforms NOP Read WriteOrdering Information Ball Fine Pitch Ball Grid Array 15 x 17 x 1.4 mm Lead-Free Package Diagram Ball Fbga 15 x 17 x 1.40 mmDocument History NXRVKN/KKVTMP VKN/AESA

Switching Waveforms

Figure 4. Read/Write/Deselect Sequence waveform for 2.0 Cycle Read Latency[30, 31, 32]

NOP

READ

WRITE

WPS

QVLD

DON’T CARE

UNDEFINED