Cypress CY7C1243V18, CY7C1241V18 Maximum Ratings, Operating Range, Electrical Characteristics

Page 21

CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND

–0.5V to +2.9V

Supply Voltage on VDDQ Relative to GND

–0.5V to + VDD

DC Applied to Outputs in High-Z

–0.5V to VDDQ + 0.3V

DC Input Voltage[13]

–0.5V to V + 0.3V

 

 

DD

Current into Outputs (LOW)

 

 

 

20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015)...

>2001V

Latch Up Current

 

 

 

>200 mA

Operating Range

 

 

 

 

 

 

 

 

 

 

Range

Ambient

V

[17]

V

[17]

Temperature (T )

 

A

 

DD

 

DDQ

Com’l

0°C to +70°C

1.8

± 0.1V

1.4V to VDD

Ind’l

–40°C to +85°C

 

 

 

 

 

 

 

 

 

 

Electrical Characteristics

Over the Operating Range [14]

DC Electrical Characteristics

Parameter

Description

 

 

Test Conditions

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

 

 

 

 

 

1.7

1.8

1.9

V

VDDQ

IO Supply Voltage

 

 

 

 

 

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 18

 

 

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 19

 

 

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = 0.1 mA, Nominal Impedance

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

 

 

 

 

 

VREF + 0.1

 

VDDQ + 0.15

V

VIL

Input LOW Voltage

 

 

 

 

 

 

 

–0.15

 

VREF – 0.1

V

IX

Input Leakage Current

GND VI VDDQ

 

 

 

2

 

2

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

2

 

2

μA

VREF

Input Reference Voltage[20]

Typical Value = 0.75V

 

 

0.68

0.75

0.95

V

IDD [21]

VDD Operating Supply

VDD = Max., IOUT = 0mA,

 

300 MHz

 

 

1040

mA

 

 

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

 

 

 

 

333 MHz

 

 

1120

mA

 

 

 

 

 

 

 

 

375 MHz

 

 

1240

mA

 

 

 

 

 

 

 

 

 

ISB1

Automatic Power down

Max. VDD, Both Ports

 

300 MHz

 

 

280

mA

 

Current

Deselected, VIN VIH or

 

 

 

 

 

 

 

 

333 MHz

 

 

300

mA

 

 

V

 

V , f = f

= 1/t

 

,

 

 

 

 

 

IN

IL

MAX

CYC

 

 

 

 

 

 

 

 

Inputs Static

 

 

 

375 MHz

 

 

310

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

AC Electrical Characteristics

Over the Operating Range [13]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VIH

Input HIGH Voltage

 

VREF + 0.2

VDDQ + 0.24

V

VIL

Input LOW Voltage

 

–0.24

VREF – 0.2

V

Notes

17.Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

18.Outputs are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.

19.Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.

20.VREF (min) = 0.68V or 0.46VDDQ, whichever is larger; VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.

21.The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-06365 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1241V18 Logic Block Diagram CY7C1256V18Doff Logic Block Diagram CY7C1245V18 Logic Block Diagram CY7C1243V18CY7C1241V18 4M x Pin ConfigurationsCY7C1256V18 4M x NC/144MCY7C1243V18 2M x CY7C1245V18 1M xWPS BWS RPS Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagWrite Operations Functional OverviewByte Write Operations Read OperationsDelay Lock Loop DLL Valid Data Indicator QvldDepth Expansion Programmable ImpedanceTruth Table Application ExampleSram #4 BUS MasterComments Write Cycle DescriptionsRemains unaltered During the data portion of a write sequenceInto the device Write cycle description table for CY7C1245V18 follows.2Written into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Controller Parameter Description Test Conditions Min Max UnitTAP Timing and Test Conditions16 TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in QDR-II+ SramPower Up Waveforms DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max Set-up TimesNOP Read Write Switching WaveformsOrdering Information Ball Fine Pitch Ball Grid Array 15 x 17 x 1.4 mm Lead-Free Ball Fbga 15 x 17 x 1.40 mm Package DiagramNXR Document HistoryVKN/KKVTMP VKN/AESA