Cypress CY7C1243V18 manual TAP AC Switching Characteristics, TAP Timing and Test Conditions16

Page 17

CY7C1241V18, CY7C1256V18

CY7C1243V18, CY7C1245V18

TAP AC Switching Characteristics

Over the Operating Range [15, 16]

Parameter

Description

Min

Max

Unit

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH

20

 

ns

tTL

TCK Clock LOW

20

 

ns

Setup Times

 

 

 

 

 

 

 

 

 

tTMSS

TMS Setup to TCK Clock Rise

5

 

ns

tTDIS

TDI Setup to TCK Clock Rise

5

 

ns

tCS

Capture Setup to TCK Rise

5

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

Output Times

 

 

 

 

 

 

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

TAP Timing and Test Conditions[16]

 

 

 

0.9V

 

 

 

 

 

 

 

 

50Ω

 

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

 

 

Z0

= 50Ω

 

 

 

 

 

CL = 20 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a) GND

Test Clock

TCK

tTMSS

0V

tTH

ALL INPUT PULSES

1.8V

0.9V

tTL

tTCYC

tTMSH

Test Mode Select

TMS

Test Data In

TDI

Test Data Out

TDO

tTDIS

tTDIH

 

tTDOV

 

 

 

 

t

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDOX

 

 

 

 

 

 

 

 

 

 

 

 

Notes

15.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

16.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

Document Number: 001-06365 Rev. *D

Page 17 of 28

[+] Feedback

Image 17
Contents Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1241V18Logic Block Diagram CY7C1256V18 Logic Block Diagram CY7C1245V18 Logic Block Diagram CY7C1243V18CY7C1241V18 4M x Pin ConfigurationsCY7C1256V18 4M x NC/144MWPS BWS RPS CY7C1243V18 2M xCY7C1245V18 1M x Negative Input Clock Input Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagWrite Operations Functional OverviewByte Write Operations Read OperationsDelay Lock Loop DLL Valid Data Indicator QvldDepth Expansion Programmable ImpedanceTruth Table Application ExampleSram #4 BUS MasterComments Write Cycle DescriptionsRemains unaltered During the data portion of a write sequenceInto the device Write cycle description table for CY7C1245V18 follows.2Written into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Controller Parameter Description Test Conditions Min Max UnitTAP Timing and Test Conditions16 TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in QDR-II+ SramPower Up Waveforms DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max Set-up TimesNOP Read Write Switching WaveformsOrdering Information Ball Fine Pitch Ball Grid Array 15 x 17 x 1.4 mm Lead-Free Ball Fbga 15 x 17 x 1.40 mm Package DiagramNXR Document HistoryVKN/KKVTMP VKN/AESA