Cypress CY7C1245V18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1241V18, CY7C1256V18

CY7C1243V18, CY7C1245V18

Identification Register Definitions

	Instruction		Value			Description
	Field	CY7C1241V18	CY7C1256V18	CY7C1243V18	CY7C1245V18	Description
	Field	CY7C1241V18	CY7C1256V18	CY7C1243V18	CY7C1245V18
	Revision	000	000	000	000	Version number.
	Number (31:29)
	Cypress Device	11010010101000111	11010010101001111	11010010101010111	11010010101100111	Defines the type
	ID (28:12)					of SRAM.
	Cypress JEDEC	00000110100	00000110100	00000110100	00000110100	Enables unique
	ID (11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an
						ID register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	109

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input/output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between
		TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input/output contents. Places the boundary scan register between
		TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input/output ring contents. Places the boundary scan register
		between TDI and TDO. Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect
		SRAM operation.

Document Number: 001-06365 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1241V18 Logic Block Diagram CY7C1256V18Doff Logic Block Diagram CY7C1243V18 Logic Block Diagram CY7C1245V18CY7C1256V18 4M x Pin ConfigurationsCY7C1241V18 4M x NC/144MCY7C1243V18 2M x CY7C1245V18 1M xWPS BWS RPS Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagByte Write Operations Functional OverviewWrite Operations Read OperationsDepth Expansion Valid Data Indicator QvldDelay Lock Loop DLL Programmable ImpedanceSram #4 Application ExampleTruth Table BUS MasterRemains unaltered Write Cycle DescriptionsComments During the data portion of a write sequenceWritten into the device. D 359 remains unaltered Write cycle description table for CY7C1245V18 follows.2Into the device Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test Conditions16Instruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in QDR-II+ SramPower Up Sequence DLL ConstraintsAC Electrical Characteristics Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Set-up TimesSwitching Waveforms NOP Read WriteOrdering Information Ball Fine Pitch Ball Grid Array 15 x 17 x 1.4 mm Lead-Free Package Diagram Ball Fbga 15 x 17 x 1.40 mmVKN/KKVTMP Document HistoryNXR VKN/AESA