Cypress CY7C1241V18 manual Power Up Sequence in QDR-II+ Sram, DLL Constraints, Power Up Waveforms

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CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

Power Up Sequence in QDR-II+ SRAM

QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. During power up, when the DOFF is tied HIGH, the DLL is locked after 2048 cycles of stable clock.

Power Up Sequence

■Apply power with DOFF tied HIGH (All other inputs can be HIGH or LOW)

❐Apply VDD before VDDQ

❐Apply VDDQ before VREF or at the same time as VREF

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the clock frequency you want.

■Provide stable power and clock (K, K) for 2048 cycles to lock the DLL.

Power Up Waveforms

Figure 2. Power Up Waveforms

K

K

VDD/VDDQ

DOFF

~ ~

	~ ~

Unstable Clock	> 2048 Stable Clock	Start Normal
Clock Start (Clock Starts after VDD/VDDQ is Stable)		Operation
Clock Start (Clock Starts after VDD/VDDQ is Stable)

VDD/VDDQ Stable (< + 0.1V DC per 50 ns)

Fix HIGH (tie to VDDQ)

Document Number: 001-06365 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideDoff Logic Block Diagram CY7C1241V18Logic Block Diagram CY7C1256V18 Logic Block Diagram CY7C1243V18 Logic Block Diagram CY7C1245V18Pin Configurations CY7C1241V18 4M xCY7C1256V18 4M x NC/144MWPS BWS RPS CY7C1243V18 2M xCY7C1245V18 1M x Negative Input Clock Input Pin DefinitionsPin Name Pin Description Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Write OperationsByte Write Operations Read OperationsValid Data Indicator Qvld Delay Lock Loop DLLDepth Expansion Programmable ImpedanceApplication Example Truth TableSram #4 BUS MasterWrite Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle description table for CY7C1245V18 follows.2 Into the deviceWritten into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test Conditions16Identification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max Set-up TimesSwitching Waveforms NOP Read WriteOrdering Information Ball Fine Pitch Ball Grid Array 15 x 17 x 1.4 mm Lead-Free Package Diagram Ball Fbga 15 x 17 x 1.40 mmDocument History NXRVKN/KKVTMP VKN/AESA