Cypress CY7C1241V18 Write cycle description table for CY7C1245V18 follows.2, Into the device

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CY7C1241V18, CY7C1256V18

CY7C1243V18, CY7C1245V18

Write Cycle Descriptions

The write cycle description table for CY7C1245V18 follows.[2, 10]

 

BWS0

 

BWS1

 

BWS2

 

BWS3

K

 

K

Comments

 

L

 

L

 

L

 

L

L–H

 

During the data portion of a write sequence, all four bytes (D[35:0]) are written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device.

 

L

 

L

 

L

 

L

L–H

During the data portion of a write sequence, all four bytes (D[35:0]) are written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device.

 

L

 

H

 

H

 

H

L–H

 

During the data portion of a write sequence, only the lower byte (D[8:0]) is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

written into the device. D[35:9] remains unaltered.

 

L

 

H

 

H

 

H

L–H

During the data portion of a write sequence, only the lower byte (D[8:0]) is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

written into the device. D[35:9] remains unaltered.

 

H

 

L

 

H

 

H

L–H

 

During the data portion of a write sequence, only the byte (D[17:9]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[8:0] and D[35:18] remain unaltered.

 

H

 

L

 

H

 

H

L–H

During the data portion of a write sequence, only the byte (D[17:9]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[8:0] and D[35:18] remain unaltered.

 

H

 

H

 

L

 

H

L–H

 

During the data portion of a write sequence, only the byte (D[26:18]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[17:0] and D[35:27] remain unaltered.

 

H

 

H

 

L

 

H

L–H

During the data portion of a write sequence, only the byte (D[26:18]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[17:0] and D[35:27] remain unaltered.

 

H

 

H

 

H

 

L

L–H

 

During the data portion of a write sequence, only the byte (D[35:27]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

L

L–H

During the data portion of a write sequence, only the byte (D[35:27]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

H

L–H

 

No data is written into the device during this portion of a write operation.

 

H

 

H

 

H

 

H

L–H

No data is written into the device during this portion of a write operation.

Document Number: 001-06365 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1241V18 Logic Block Diagram CY7C1256V18Doff Logic Block Diagram CY7C1243V18 Logic Block Diagram CY7C1245V18Pin Configurations CY7C1241V18 4M xCY7C1256V18 4M x NC/144MCY7C1243V18 2M x CY7C1245V18 1M xWPS BWS RPS Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Write OperationsByte Write Operations Read OperationsValid Data Indicator Qvld Delay Lock Loop DLLDepth Expansion Programmable ImpedanceApplication Example Truth TableSram #4 BUS MasterWrite Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle description table for CY7C1245V18 follows.2 Into the deviceWritten into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test Conditions16Identification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max Set-up TimesSwitching Waveforms NOP Read WriteOrdering Information Ball Fine Pitch Ball Grid Array 15 x 17 x 1.4 mm Lead-Free Package Diagram Ball Fbga 15 x 17 x 1.40 mmDocument History NXRVKN/KKVTMP VKN/AESA