Cypress CY7C1243V18 manual Pin Configurations, CY7C1241V18 4M x, CY7C1256V18 4M x, NC/144M

Page 4

CY7C1241V18, CY7C1256V18

CY7C1243V18, CY7C1245V18

Pin Configurations

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1241V18 (4M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

1

NC/144M

A

CQ

WPS

NWS

K

RPS

B

NC

A

NC/288M

K

0

A

NC

Q3

NWS

C

NC

VSS

A

NC

A

VSS

NC

D3

D

NC

D4

NC

VSS

NC

E

NC

Q4

VDDQ

VSS

VDDQ

NC

D2

Q2

F

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

G

NC

D5

Q5

VDDQ

VDD

VSS

VDD

VDDQ

NC

H

VREF

VDDQ

VDD

VSS

VDD

VDDQ

VREF

ZQ

DOFF

J

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q1

D1

K

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

L

NC

Q6

D6

VDDQ

VSS

VDDQ

NC

Q0

M

NC

VSS

NC

D0

N

NC

D7

NC

VSS

A

VSS

NC

P

NC

Q7

A

QVLD

A

NC

R

TDO

TCK

A

NC

A

TMS

TDI

CY7C1256V18 (4M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

NC

NC/144M

A

CQ

WPS

K

RPS

B

NC

A

NC/288M

K

0

A

NC

Q4

BWS

C

NC

VSS

A

NC

A

VSS

NC

D4

D

NC

D5

NC

VSS

NC

E

NC

Q5

VDDQ

VSS

VDDQ

NC

D3

Q3

F

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

G

NC

D6

Q6

VDDQ

VDD

VSS

VDD

VDDQ

NC

H

VREF

VDDQ

VDD

VSS

VDD

VDDQ

VREF

ZQ

DOFF

J

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q2

D2

K

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

L

NC

Q7

D7

VDDQ

VSS

VDDQ

NC

Q1

M

NC

VSS

NC

D1

N

NC

D8

NC

VSS

A

VSS

NC

P

NC

Q8

A

QVLD

A

NC

D0

Q0

R

TDO

TCK

A

NC

A

TMS

TDI

Document Number: 001-06365 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1256V18 Logic Block Diagram CY7C1241V18Doff Logic Block Diagram CY7C1243V18 Logic Block Diagram CY7C1245V18Pin Configurations CY7C1241V18 4M xCY7C1256V18 4M x NC/144MCY7C1245V18 1M x CY7C1243V18 2M xWPS BWS RPS Pin Name Pin Description Pin DefinitionsNegative Input Clock Input Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Write OperationsByte Write Operations Read OperationsValid Data Indicator Qvld Delay Lock Loop DLLDepth Expansion Programmable ImpedanceApplication Example Truth TableSram #4 BUS MasterWrite Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle description table for CY7C1245V18 follows.2 Into the deviceWritten into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test Conditions16Identification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max Set-up TimesSwitching Waveforms NOP Read WriteOrdering Information Ball Fine Pitch Ball Grid Array 15 x 17 x 1.4 mm Lead-Free Package Diagram Ball Fbga 15 x 17 x 1.40 mmDocument History NXRVKN/KKVTMP VKN/AESA