Cypress CY7C1256V18, CY7C1241V18 Logic Block Diagram CY7C1243V18, Logic Block Diagram CY7C1245V18

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CY7C1241V18, CY7C1256V18

CY7C1243V18, CY7C1245V18

Logic Block Diagram (CY7C1243V18)

D[17:0]

Address

A(18:0)

CLK

Gen.

DOFF

VREF

WPS

Control

BWS

Logic

[1:0]

Write

Address

Reg

Decode

512K x

Decode

WriteAdd.

18Array

ReadAdd.

Logic

Control

Read Data Reg.

Reg.

19A(18:0)

RPS

Q[17:0]

QVLD

Logic Block Diagram (CY7C1245V18)

D[35:0]

Address

A(17:0)

CLK

Gen.

DOFF

VREF

WPS

Control

BWS

Logic

[3:0]

Document Number: 001-06365 Rev. *D

Write

Address

Reg

Decode

256K x

Decode

WriteAdd.

36Array

ReadAdd.

Logic

Control

Read Data Reg.

144

Reg.

18A(17:0)

RPS

Q[35:0]

QVLD

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1241V18 Logic Block Diagram CY7C1256V18Doff Logic Block Diagram CY7C1245V18 Logic Block Diagram CY7C1243V18NC/144M Pin ConfigurationsCY7C1241V18 4M x CY7C1256V18 4M xCY7C1243V18 2M x CY7C1245V18 1M xWPS BWS RPS Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsProgrammable Impedance Valid Data Indicator QvldDelay Lock Loop DLL Depth ExpansionBUS Master Application ExampleTruth Table Sram #4During the data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredInto the device. D 80 and D 3518 remain unaltered Write cycle description table for CY7C1245V18 follows.2Into the device Written into the device. D 359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State DiagramParameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP ControllerTAP Timing and Test Conditions16 TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II+ SramPower Up Sequence Power Up WaveformsMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical CharacteristicsParameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and WaveformsSet-up Times Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxNOP Read Write Switching WaveformsOrdering Information Ball Fine Pitch Ball Grid Array 15 x 17 x 1.4 mm Lead-Free Ball Fbga 15 x 17 x 1.40 mm Package DiagramVKN/AESA Document HistoryNXR VKN/KKVTMP