Cypress CY7C1241V18 TAP Controller Block Diagram, TAP Electrical Characteristics, Gnd ≤ Vi ≤ Vdd

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CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

TAP Controller Block Diagram


																						0
																						0

																			Bypass Register
TDI						Selection																						Selection
TDI						Selection													2		1	0						Selection
						Circuitry																						Circuitry
						Circuitry								Instruction Register														Circuitry
														Instruction Register

												31		30	29	.	.		2		1	0
												31		30	29	.	.		2		1	0

														Identification Register

												108		.	.	.	.		2		1	0



														Boundary Scan Register

	TCK

																TAP Controller

	TMS
	TMS

TDO

TAP Electrical Characteristics

Over the Operating Range[12, 13, 14]

Parameter	Description	Test Conditions	Min	Max	Unit
VOH1	Output HIGH Voltage	IOH = −2.0 mA	1.4		V
VOH2	Output HIGH Voltage	IOH = −100 μA	1.6		V
VOL1	Output LOW Voltage	IOL = 2.0 mA		0.4	V
VOL2	Output LOW Voltage	IOL = 100 μA		0.2	V
VIH	Input HIGH Voltage		0.65VDD	VDD + 0.3	V
VIL	Input LOW Voltage		–0.3	0.35VDD	V
IX	Input and Output Load Current	GND ≤ VI ≤ VDD	–5	5	μA

Notes

12.These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in “Electrical Characteristics” on page 21.

13.Overshoot: VIH(AC) < VDDQ + 0.3V (pulse width less than tCYC/2). Undershoot: VIL(AC) > − 0.3V (pulse width less than tCYC/2).

14.All voltage refers to Ground.

Document Number: 001-06365 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1256V18 Logic Block Diagram CY7C1241V18Doff Logic Block Diagram CY7C1243V18 Logic Block Diagram CY7C1245V18Pin Configurations CY7C1241V18 4M xCY7C1256V18 4M x NC/144MCY7C1245V18 1M x CY7C1243V18 2M xWPS BWS RPS Pin Name Pin Description Pin DefinitionsNegative Input Clock Input Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Write OperationsByte Write Operations Read OperationsValid Data Indicator Qvld Delay Lock Loop DLLDepth Expansion Programmable ImpedanceApplication Example Truth TableSram #4 BUS MasterWrite Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle description table for CY7C1245V18 follows.2 Into the deviceWritten into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test Conditions16Identification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max Set-up TimesSwitching Waveforms NOP Read WriteOrdering Information Ball Fine Pitch Ball Grid Array 15 x 17 x 1.4 mm Lead-Free Package Diagram Ball Fbga 15 x 17 x 1.40 mmDocument History NXRVKN/KKVTMP VKN/AESA