Cypress CY7C1475V25 TAP AC Switching Characteristics, Parameter Description Min Max Unit Clock

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CY7C1471V25

CY7C1473V25

CY7C1475V25

TAP AC Switching Characteristics

Over the Operating Range[10, 11]

Parameter

Description

Min

Max

Unit

Clock

 

 

 

 

 

 

 

 

 

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH Time

20

 

ns

tTL

TCK Clock LOW Time

20

 

ns

Output Times

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

Setup Times

 

 

 

 

tTMSS

TMS Setup to TCK Clock Rise

5

 

ns

tTDIS

TDI Setup to TCK Clock Rise

5

 

ns

tCS

Capture Setup to TCK Rise

5

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

Notes

10.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 11.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

Document #: 38-05287 Rev. *I

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Contents Features Functional Description1Selection Guide 133 MHz 100 MHz UnitLogic Block Diagram CY7C1471V25 2M x Logic Block Diagram CY7C1473V25 4M xLogic Block Diagram CY7C1475V25 1M x Pin Configurations Pin Tqfp Pinout CY7C1471V25CY7C1473V25 CY7C1473V25 4M x ADV/LD Pin Definitions Single Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Address Operation Truth TableUsed Function Truth Table for Read/WriteFunction BW b BW a TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers TAP Instruction SetTAP Timing BypassTAP AC Switching Characteristics Parameter Description Min Max Unit ClockOutput Times Hold Times8V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Scan Register Sizes Identification CodesRegister Name Bit Size Instruction Code DescriptionBoundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID Boundary Scan Exit Order 1M x P10W10 V10Maximum Ratings Electrical CharacteristicsOperating Range Thermal Resistance CapacitanceAC Test Loads and Waveforms Switching Characteristics Setup TimesParameter Description 133 MHz 100 MHz Unit Min CENRite Switching WaveformsRead Address QA2Stall Stall NOPDON’T Care Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. Description of Change Date Document HistoryVKN VKN/AESA