Cypress CY7C1473V25, CY7C1475V25, CY7C1471V25 manual TAP Timing, Bypass

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CY7C1471V25

CY7C1473V25

CY7C1475V25

signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH).

The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls.

Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

1

2

 

3

Test Clock

 

 

 

(TCK )

tTH

tTL

tCY C

 

tTM SS

tTM SH

 

 

Test M ode Select (TM S)

tTDIS tTDIH

Test Data-In (TDI)

Test Data-Out (TDO)

DON’T CA RE

4

5

6

 

 

 

tTDO V

tTDOX

UNDEFINED

Document #: 38-05287 Rev. *I

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Contents 133 MHz 100 MHz Unit FeaturesFunctional Description1 Selection GuideLogic Block Diagram CY7C1473V25 4M x Logic Block Diagram CY7C1471V25 2M xLogic Block Diagram CY7C1475V25 1M x CY7C1471V25 Pin Configurations Pin Tqfp PinoutCY7C1473V25 CY7C1473V25 4M x ADV/LD Pin Definitions Functional Overview Single Read AccessesBurst Read Accesses Single Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Truth Table Address OperationUsed Truth Table for Read/Write FunctionFunction BW b BW a TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set TAP RegistersBypass TAP TimingHold Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Output TimesTAP DC Electrical Characteristics And Operating Conditions 8V TAP AC Test Conditions5V TAP AC Test Conditions Instruction Code Description Scan Register SizesIdentification Codes Register Name Bit SizeBoundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID V10 Boundary Scan Exit Order 1M xP10 W10Electrical Characteristics Maximum RatingsOperating Range Capacitance Thermal ResistanceAC Test Loads and Waveforms CEN Switching CharacteristicsSetup Times Parameter Description 133 MHz 100 MHz Unit MinSwitching Waveforms RiteRead Stall NOP AddressQA2 StallDON’T Care Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Orig. Description of Change DateVKN/AESA VKN
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