Cypress CY7C1473V25 manual Scan Register Sizes, Identification Codes, Register Name Bit Size

Page 18

 

 

 

 

 

 

 

 

 

CY7C1471V25

 

 

 

 

 

 

 

 

 

 

CY7C1473V25

 

 

 

 

 

 

 

 

 

 

CY7C1475V25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Scan Register Sizes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Name

 

 

Bit Size (x36)

Bit Size (x18)

 

Bit Size (x72)

 

 

 

 

 

 

 

 

 

 

Instruction

 

3

3

 

3

 

 

 

 

 

 

 

 

 

 

Bypass

 

1

1

 

1

 

 

 

 

 

 

 

 

 

 

ID

 

32

32

 

32

 

 

 

 

 

 

 

 

 

Boundary Scan Order – 165FBGA

71

52

 

-

 

 

 

 

 

 

 

 

 

 

Boundary Scan Order – 209BGA

 

-

-

 

110

 

 

 

 

 

 

 

 

 

 

Identification Codes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

 

 

Code

 

 

Description

 

 

EXTEST

 

 

000

 

Captures IO ring contents. Places the boundary scan register between TDI and

 

 

 

 

 

 

 

TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1

 

 

 

 

 

 

 

compliant.

 

 

 

 

IDCODE

 

 

001

 

Loads the ID register with the vendor ID code and places the register between TDI

 

 

 

 

 

 

 

and TDO. This operation does not affect SRAM operations.

 

SAMPLE Z

 

 

010

 

Captures IO ring contents. Places the boundary scan register between TDI and

 

 

 

 

 

 

 

TDO. Forces all SRAM output drivers to a High-Z state.

 

 

RESERVED

 

 

011

 

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

 

 

SAMPLE/PRELOAD

 

 

100

 

Captures IO ring contents. Places the boundary scan register between TDI and

 

 

 

 

 

 

 

TDO. Does not affect SRAM operation. This instruction does not implement 1149.1

 

 

 

 

 

 

 

preload function and is therefore not 1149.1 compliant.

 

 

RESERVED

 

 

101

 

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

 

 

 

RESERVED

 

 

110

 

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

 

 

BYPASS

 

 

111

 

Places the bypass register between TDI and TDO. This operation does not affect

 

 

 

 

 

 

 

SRAM operation.

 

 

 

 

Document #: 38-05287 Rev. *I

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Contents Selection Guide FeaturesFunctional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1471V25 2M x Logic Block Diagram CY7C1473V25 4M xLogic Block Diagram CY7C1475V25 1M x Pin Configurations Pin Tqfp Pinout CY7C1471V25CY7C1473V25 CY7C1473V25 4M x ADV/LD Pin Definitions Single Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Truth Table Address OperationUsed Truth Table for Read/Write FunctionFunction BW b BW a TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers TAP Instruction SetTAP Timing BypassOutput Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Hold TimesTAP DC Electrical Characteristics And Operating Conditions 8V TAP AC Test Conditions5V TAP AC Test Conditions Register Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBoundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID W10 Boundary Scan Exit Order 1M xP10 V10Electrical Characteristics Maximum RatingsOperating Range Capacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description 133 MHz 100 MHz Unit Min Switching CharacteristicsSetup Times CENSwitching Waveforms RiteRead Stall AddressQA2 Stall NOPDON’T Care Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. Description of Change Date Document HistoryVKN VKN/AESA
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