Cypress manual Logic Block Diagram CY7C1471V25 2M x, Logic Block Diagram CY7C1473V25 4M x

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									CY7C1471V25
									CY7C1473V25
									CY7C1475V25
Logic Block Diagram – CY7C1471V25 (2M x 36)
	A0, A1, A	ADDRESS	A1			A1'
	A0, A1, A	REGISTER
		REGISTER		D1	Q1
	MODE		A0	D0	Q0	A0'
		CE	ADV/LD		BURST
CLK	C	CE			LOGIC
CLK	C				LOGIC
CEN			C
			WRITE ADDRESS
			REGISTER							O
										O
										U
										T
								S	D	P
								S	A	U
								E	T	T
	ADV/LD							N	A
	BW A						MEMORY	S		B
	BW A		WRITE REGISTRY			WRITE	ARRAY	E	S	U	DQs
			WRITE REGISTRY			WRITE	ARRAY	E	S	U	DQs
	BW B		AND DATA COHERENCY			DRIVERS		A	T	F	DQP A
	BW C		CONTROL LOGIC					A	E	F	DQP B
			CONTROL LOGIC					M	E	F	DQP B
								M	E	E	DQP C
	BW D							P	R	R	DQP C
								P	R	R	DQP D
								S	I	S
								S	I	S
	WE								N		E
									G
							INPUT	E
							REGISTER	E
	OE						REGISTER
	OE	READ LOGIC
	CE1	READ LOGIC
	CE1
	CE2
	CE3		SLEEP
	ZZ		SLEEP
	ZZ	CONTROL
		CONTROL
Logic Block Diagram – CY7C1473V25 (4M x 18)

A0, A1, A

ADDRESS

A1

A1'

REGISTER

D1

Q1

MODE

A0

D0

Q0 A0'

CE

ADV/LD

BURST

CLK

C

LOGIC

CEN

C

WRITE ADDRESS

REGISTER

O

U

T

S

D

P

A

U

E

T

T

ADV/LD

N

A

BW A

WRITE

MEMORY

S

B

WRITE REGISTRY

ARRAY

E

S

U

DQs

BW B

AND DATA COHERENCY

DRIVERS

A

T

F

DQPA

CONTROL LOGIC

E

F

DQPB

M

E

E

P

R

R

WE

S

I

S

E

N

G

INPUT

E

REGISTER

OE

READ LOGIC

CE1

CE2

CE3

ZZ

SLEEP

CONTROL

Document #: 38-05287 Rev. *I

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Contents Selection Guide FeaturesFunctional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1471V25 2M x Logic Block Diagram CY7C1473V25 4M xLogic Block Diagram CY7C1475V25 1M x Pin Configurations Pin Tqfp Pinout CY7C1471V25CY7C1473V25 CY7C1473V25 4M x ADV/LD Pin Definitions Single Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Used Truth TableAddress Operation Function BW b BW a Truth Table for Read/WriteFunction Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Registers TAP Instruction SetTAP Timing BypassOutput Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions8V TAP AC Test Conditions Register Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBit # Ball ID Boundary Scan Exit Order 2M xBoundary Scan Exit Order 4M x W10 Boundary Scan Exit Order 1M xP10 V10Operating Range Electrical CharacteristicsMaximum Ratings AC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description 133 MHz 100 MHz Unit Min Switching CharacteristicsSetup Times CENRead Switching WaveformsRite Stall AddressQA2 Stall NOPDON’T Care Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. Description of Change Date Document HistoryVKN VKN/AESA