Cypress CY7C1475V25 Boundary Scan Exit Order 2M x, Boundary Scan Exit Order 4M x, Bit # Ball ID

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CY7C1471V25

CY7C1473V25

CY7C1475V25

Boundary Scan Exit Order (2M x 36)

Bit #	165-Ball ID		Bit #	165-Ball ID		Bit #	165-Ball ID		Bit #	165-Ball ID
1	C1		21	R3		41	J11		61	B7

2	D1		22	P2		42	K10		62	B6

3	E1		23	R4		43	J10		63	A6

4	D2		24	P6		44	H11		64	B5

5	E2		25	R6		45	G11		65	A5

6	F1		26	R8		46	F11		66	A4

7	G1		27	P3		47	E11		67	B4

8	F2		28	P4		48	D10		68	B3

9	G2		29	P8		49	D11		69	A3

10	J1		30	P9		50	C11		70	A2

11	K1		31	P10		51	G10		71	B2

12	L1		32	R9		52	F10

13	J2		33	R10		53	E10

14	M1		34	R11		54	A9

15	N1		35	N11		55	B9

16	K2		36	M11		56	A10

17	L2		37	L11		57	B10

18	M2		38	M10		58	A8

19	R1		39	L10		59	B8

20	R2		40	K11		60	A7

Boundary Scan Exit Order (4M x 18)

Bit #	165-Ball ID		Bit #	165-Ball ID		Bit #	165-Ball ID		Bit #	165-Ball ID
1	D2		14	R4		27	L10		40	B10

2	E2		15	P6		28	K10		41	A8

3	F2		16	R6		29	J10		42	B8

4	G2		17	R8		30	H11		43	A7

5	J1		18	P3		31	G11		44	B7

6	K1		19	P4		32	F11		45	B6

7	L1		20	P8		33	E11		46	A6

8	M1		21	P9		34	D11		47	B5

9	N1		22	P10		35	C11		48	A4

10	R1		23	R9		36	A11		49	B3

11	R2		24	R10		37	A9		50	A3

12	R3		25	R11		38	B9		51	A2

13	P2		26	M10		39	A10		52	B2

Document #: 38-05287 Rev. *I

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Contents 133 MHz 100 MHz Unit FeaturesFunctional Description1 Selection GuideLogic Block Diagram CY7C1473V25 4M x Logic Block Diagram CY7C1471V25 2M xLogic Block Diagram CY7C1475V25 1M x CY7C1471V25 Pin Configurations Pin Tqfp PinoutCY7C1473V25 CY7C1473V25 4M x ADV/LD Pin Definitions Functional Overview Single Read AccessesBurst Read Accesses Single Write AccessesLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Address Operation Truth TableUsed Function Truth Table for Read/WriteFunction BW b BW a TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set TAP RegistersBypass TAP TimingHold Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Output Times8V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Instruction Code Description Scan Register SizesIdentification Codes Register Name Bit SizeBoundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID V10 Boundary Scan Exit Order 1M xP10 W10Maximum Ratings Electrical CharacteristicsOperating Range Thermal Resistance CapacitanceAC Test Loads and Waveforms CEN Switching CharacteristicsSetup Times Parameter Description 133 MHz 100 MHz Unit MinRite Switching WaveformsRead Stall NOP AddressQA2 StallDON’T Care Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Orig. Description of Change DateVKN/AESA VKN