Cypress CY7C1473V25, CY7C1475V25, CY7C1471V25 manual Ball Fbga 14 x 22 x 1.76 mm

Page 30

CY7C1471V25

CY7C1473V25

CY7C1475V25

Package Diagrams (continued)

Figure 6. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167

51-85167-**

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05287 Rev. *I

Page 30 of 32

© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

[+] Feedback

Page 29 Page 31
Image 30
Page 29 Page 31
Contents Selection Guide FeaturesFunctional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1471V25 2M x Logic Block Diagram CY7C1473V25 4M xLogic Block Diagram CY7C1475V25 1M x Pin Configurations Pin Tqfp Pinout CY7C1471V25CY7C1473V25 CY7C1473V25 4M x ADV/LD Pin Definitions Single Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Truth Table Address OperationUsed Truth Table for Read/Write FunctionFunction BW b BW a TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers TAP Instruction SetTAP Timing BypassOutput Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Hold TimesTAP DC Electrical Characteristics And Operating Conditions 8V TAP AC Test Conditions5V TAP AC Test Conditions Register Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBoundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID W10 Boundary Scan Exit Order 1M xP10 V10Electrical Characteristics Maximum RatingsOperating Range Capacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description 133 MHz 100 MHz Unit Min Switching CharacteristicsSetup Times CENSwitching Waveforms RiteRead Stall AddressQA2 Stall NOPDON’T Care Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. Description of Change Date Document HistoryVKN VKN/AESA
Top Page Image Contents