Cypress CY7C1471V25, CY7C1475V25 manual CY7C1473V25

Page 5

CY7C1471V25

CY7C1473V25

CY7C1475V25

Pin Configurations (continued)

100-Pin TQFP Pinout

BYTE B

VDDQ

VSS

NC NC

DQB

VSS VDDQ

DQB DQB

VDD

VSS

DQB

VDDQ

VSS

DQB DQB

DQPB

VSS VDDQ

A		A		CE	CE		NC		NC	BW	BW	CE	V		V		CLK		WE		CEN		OE		ADV/LD		A		A		A	A


				1	2					B	A	3		DD		SS
														DD		SS



100		99		98	97		96		95	94	93	92	91		90		89		88	87			86	85			84		83		82	81
1																																80
2																																79
3																																78
4																																77
5																																76
6																																75
7																																74
8																																73
9																																72
10																																71
11																																70
12																																69
13																																68
14																																67
15											CY7C1473V25																					66
16											CY7C1473V25																					65
17																																64
18																																63
19																																62
20																																61
21																																60
22																																59
23																																58
24																																57
25																																56
26																																55
27																																54
28																																53
29																																52
30																																51
31		32		33	34		35		36	37	38	39	40		41		42		43	44			45	46			47		48		49	50


	MODE		A	A		A		A	A1	A0	NC/288M	NC/144M		V		V		A	A			A	A			A		A		A	A		A
														SS		DD

VDDQ

VSS

NC DQPA

DQA DQA

VSS

VDDQ

DQA DQA

VSS

VDD

DQA DQA

VDDQ

VSS

DQA DQA NC

VSS

VDDQ

BYTE A

Document #: 38-05287 Rev. *I

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Contents Functional Description1 FeaturesSelection Guide 133 MHz 100 MHz UnitLogic Block Diagram CY7C1473V25 4M x Logic Block Diagram CY7C1471V25 2M xLogic Block Diagram CY7C1475V25 1M x CY7C1471V25 Pin Configurations Pin Tqfp PinoutCY7C1473V25 CY7C1473V25 4M x ADV/LD Pin Definitions Burst Read Accesses Single Read AccessesSingle Write Accesses Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Used Truth TableAddress Operation Function BW b BW a Truth Table for Read/WriteFunction Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set TAP RegistersBypass TAP TimingParameter Description Min Max Unit Clock TAP AC Switching CharacteristicsOutput Times Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions8V TAP AC Test Conditions Identification Codes Scan Register SizesRegister Name Bit Size Instruction Code DescriptionBit # Ball ID Boundary Scan Exit Order 2M xBoundary Scan Exit Order 4M x P10 Boundary Scan Exit Order 1M xW10 V10Operating Range Electrical CharacteristicsMaximum Ratings AC Test Loads and Waveforms CapacitanceThermal Resistance Setup Times Switching CharacteristicsParameter Description 133 MHz 100 MHz Unit Min CENRead Switching WaveformsRite QA2 AddressStall Stall NOPDON’T Care Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Orig. Description of Change DateVKN/AESA VKN