Cypress CY7C1475V25, CY7C1473V25 manual Interleaved Burst Address Table Mode = Floating or VDD

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CY7C1471V25

CY7C1473V25

CY7C1475V25

Because the CY7C1471V25, CY7C1473V25, and CY7C1475V25 are common IO devices, data must not be driven into the device while the outputs are active. The OE can be deasserted HIGH before presenting data to the DQs and DQPX inputs. This tri-states the output drivers. As a safety precaution, DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1471V25, CY7C1473V25, and CY7C1475V25 have an on-chip burst counter that enables the user to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in the Single Write Access section. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incre- mented. The correct BWX inputs must be driven in each cycle of the Burst Write, to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table (MODE = Floating or VDD)

First	Second	Third	Fourth
Address	Address	Address	Address
A1: A0	A1: A0	A1: A0	A1: A0
00	01	10	11

01	00	11	10

10	11	00	01

11	10	01	00

Linear Burst Address Table (MODE = GND)

First	Second	Third	Fourth
Address	Address	Address	Address
A1: A0	A1: A0	A1: A0	A1: A0
00	01	10	11

01	10	11	00

10	11	00	01

11	00	01	10

ZZ Mode Electrical Characteristics

Parameter	Description	Test Conditions	Min	Max	Unit

IDDZZ	Sleep mode standby current	ZZ > VDD – 0.2V		120	mA
tZZS	Device operation to ZZ	ZZ > VDD – 0.2V		2tCYC	ns
tZZREC	ZZ recovery time	ZZ < 0.2V	2tCYC		ns
tZZI	ZZ active to sleep current	This parameter is sampled		2tCYC	ns
tRZZI	ZZ Inactive to exit sleep current	This parameter is sampled	0		ns

Document #: 38-05287 Rev. *I

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Contents Selection Guide FeaturesFunctional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1471V25 2M x Logic Block Diagram CY7C1473V25 4M xLogic Block Diagram CY7C1475V25 1M x Pin Configurations Pin Tqfp Pinout CY7C1471V25CY7C1473V25 CY7C1473V25 4M x ADV/LD Pin Definitions Single Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Address Operation Truth TableUsed Function Truth Table for Read/WriteFunction BW b BW a TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers TAP Instruction SetTAP Timing BypassOutput Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Hold Times8V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Register Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBoundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID W10 Boundary Scan Exit Order 1M xP10 V10Maximum Ratings Electrical CharacteristicsOperating Range Thermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description 133 MHz 100 MHz Unit Min Switching CharacteristicsSetup Times CENRite Switching WaveformsRead Stall AddressQA2 Stall NOPDON’T Care Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. Description of Change Date Document HistoryVKN VKN/AESA