Cypress CY7C1473V25, CY7C1471V25 manual Logic Block Diagram CY7C1475V25 1M x

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CY7C1471V25

 

 

 

 

 

 

 

 

 

 

 

CY7C1473V25

 

 

 

 

 

 

 

 

 

 

 

CY7C1475V25

Logic Block Diagram – CY7C1475V25 (1M x 72)

 

 

 

 

 

 

 

 

A0, A1, A

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

REGISTER 0

A1

 

 

A1'

 

 

 

 

 

 

 

 

D1

Q1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MODE

 

 

A0

D0

BURST Q0 A0'

 

 

 

 

 

 

 

 

 

ADV/LD

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

C

 

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

CEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE ADDRESS

 

WRITE ADDRESS

 

 

 

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

O

 

 

 

 

 

 

 

 

 

 

 

U

 

U

 

 

 

 

 

 

 

 

 

 

 

T

 

T

 

 

ADV/LD

 

 

 

 

 

 

 

S

P

D

P

 

 

 

 

 

 

 

 

 

E

U

A

U

 

 

BW a

 

 

 

 

 

 

 

N

T

T

T

 

 

 

 

 

 

 

 

MEMORY

S

R

A

B

 

 

BW b

 

 

 

 

 

WRITE

E

S

DQ s

 

 

 

 

 

 

ARRAY

 

E

U

 

BW c

 

 

WRITE REGISTRY

 

 

DRIVERS

 

A

G

T

F

DQ Pa

 

BW d

 

AND DATA COHERENCY

 

 

 

M

I

E

F

DQ Pb

 

 

 

 

 

P

S

E

E

 

BW e

 

 

CONTROL LOGIC

 

 

 

 

S

T

R

R

DQ Pc

 

BW f

 

 

 

 

 

 

 

 

E

I

S

DQ Pd

 

 

 

 

 

 

 

 

 

R

N

 

 

BW g

 

 

 

 

 

 

 

 

S

G

 

DQ Pe

 

 

 

 

 

 

 

 

 

E

E

 

BW h

 

 

 

 

 

 

 

 

 

DQ Pf

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ Pg

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ Ph

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INPUT

 

 

INPUT

E

 

 

 

 

 

 

 

 

 

REGISTER 1 E

 

 

REGISTER 0

 

 

OE

READ LOGIC

 

 

 

 

 

 

 

 

 

 

CE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

 

 

 

 

 

CE3

 

 

 

 

 

 

 

 

 

 

 

 

 

ZZ

Sleep Control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-05287 Rev. *I

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Contents 133 MHz 100 MHz Unit FeaturesFunctional Description1 Selection GuideLogic Block Diagram CY7C1473V25 4M x Logic Block Diagram CY7C1471V25 2M xLogic Block Diagram CY7C1475V25 1M x CY7C1471V25 Pin Configurations Pin Tqfp PinoutCY7C1473V25 CY7C1473V25 4M x ADV/LD Pin Definitions Functional Overview Single Read AccessesBurst Read Accesses Single Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Truth Table Address OperationUsed Truth Table for Read/Write FunctionFunction BW b BW a TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set TAP RegistersBypass TAP TimingHold Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Output TimesTAP DC Electrical Characteristics And Operating Conditions 8V TAP AC Test Conditions5V TAP AC Test Conditions Instruction Code Description Scan Register SizesIdentification Codes Register Name Bit SizeBoundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID V10 Boundary Scan Exit Order 1M xP10 W10Electrical Characteristics Maximum RatingsOperating Range Capacitance Thermal ResistanceAC Test Loads and Waveforms CEN Switching CharacteristicsSetup Times Parameter Description 133 MHz 100 MHz Unit MinSwitching Waveforms RiteRead Stall NOP AddressQA2 StallDON’T Care Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Orig. Description of Change DateVKN/AESA VKN
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