Cypress CY7C1473BV25 manual Ieee 1149.1 Serial Boundary Scan Jtag, TAP Controller State Diagram

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CY7C1471BV25 CY7C1473BV25, CY7C1475BV25

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 incorporate a serial boundary scan Test Access Port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V IO logic levels.

The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 contain a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, tie TCK LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO must be left unconnected. During power up, the device comes up in a reset state, which does not interfere with the operation of the device.

Figure 3. TAP Controller State Diagram

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test Mode Select (TMS)

The TMS input gives commands to the TAP controller and is sampled on the rising edge of TCK. You can leave this ball unconnected if the TAP is not used. The ball is pulled up inter- nally, resulting in a logic HIGH level.

Test Data In (TDI)

The TDI ball serially inputs information into the registers and is connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.)

Test Data Out (TDO)

The TDO output ball serially clocks data out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK.

1

0

TEST-LOGIC

RESET

0

RUN-TEST/ 1

IDLE

SELECT

1

SELECT

1

DR-SCA N

 

IR-SCA N

 

0

 

0

 

TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)

Figure 4. TAP Controller Block Diagram

 

1

 

CA PTURE-DR

 

 

 

1

 

CA PTURE-IR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SHIFT-DR

0

 

 

 

 

SHIFT-IR

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

1

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

1

 

 

 

EXIT1-DR

 

 

EXIT1-IR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PA USE-DR

0

 

 

 

 

PA USE-IR

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

1

 

 

 

 

0

 

 

 

 

 

 

0

 

 

 

 

 

 

EXIT2-DR

 

 

 

EXIT2-IR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UPDA TE-DR

 

 

 

 

 

UPDA TE-IR

 

 

 

 

 

 

 

 

 

 

 

 

TDI

Selection Circuitry

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bypass Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

1

0

 

 

Selection

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Register

 

 

 

 

 

 

 

 

Circuitry

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

30

29

.

.

.

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Identification Register

 

 

 

 

 

 

 

 

 

 

 

 

x

.

.

.

.

.

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Boundary Scan Register

 

TDO

 

1

0

 

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCK

TAP CONTROLLER

TM S

The 0/1 next to each state represents the value of TMS at the rising edge of TCK.

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating.

During power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

Document #: 001-15013 Rev. *E

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Contents Selection Guide Functional Description FeaturesDescription 133 MHz 100 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1473BV25 4M x Logic Block Diagram CY7C1471BV25 2M xLogic Block Diagram CY7C1475BV25 1M x CY7C1471BV25 Pin ConfigurationsCY7C1473BV25 CY7C1473BV25 4M x Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV25 2M xNC/1G Ball Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV25 1M ×Power Supply Inputs to the Core of the Device Mode Input. Selects the Burst Order of the DevicePower Supply for the IO Circuitry Pin Definitions Name DescriptionPin Definitions Functional OverviewName Description TDIFirst Second Third Fourth Address A1 A0 ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Operation Address Truth TableUsed Function Truth Table for Read/WriteIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Registers TAP Timing TAP DC Electrical Characteristics And Operating Conditions TAP AC Switching Characteristics5V TAP AC Test Conditions Identification Codes Instruction Description Scan Register Sizes Register Name Bit SizeBoundary Scan Exit Order 4M x Bit # Ball ID Boundary Scan Exit Order 2M x Bit # Ball IDBit # Ball ID Boundary Scan Exit Order 1M x Bit # Ball ID Maximum Ratings Electrical CharacteristicsOperating Range Range AmbientThermal Resistance CapacitanceParameter Description Test Conditions Tqfp Fbga Unit Setup Times Switching CharacteristicsParameter Description 133 MHz 100 MHz Unit Min Max Output TimesRead RiteAddress Switching WaveformsStall ZZ Mode Timing Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Orig. Description of Change Date

CY7C1475BV25, CY7C1473BV25, CY7C1471BV25 specifications

Cypress Semiconductor, a leader in specialized memory solutions, offers a range of high-performance SRAM products, including the CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25. These devices are designed to provide high-speed data processing capabilities along with impressive power efficiency, making them ideal choices for a variety of applications in telecommunications, networking, automotive, and consumer electronics.

The CY7C1471BV25 features a 1-Mbit density, while the CY7C1473BV25 and CY7C1475BV25 support densities of 3-Mbits and 5-Mbits respectively. All three models utilize a 3.3V power supply, and deliver fast access times of 5 ns (for CY7C1471BV25) and 6 ns (for CY7C1473BV25 and CY7C1475BV25). This rapid access enables quicker data retrieval and overall enhanced system performance.

One of the standout features of these SRAM devices is their asynchronous operation, which allows for straightforward integration into existing systems without the need for complex timing protocols. They can be easily interfaced with various microcontrollers and digital signal processors, providing flexibility and ease of use. Additionally, the devices are available in multiple package options, including the widely used TSOP and BGA formats, enabling designers to choose the best fit for their specific layouts.

In terms of technology, these SRAMs leverage advanced CMOS manufacturing processes, which contribute to their low power consumption and high reliability. With sleep modes and low standby current, they are particularly suited for battery-operated devices that demand energy efficiency.

Cypress products are renowned for their reliability and robustness, ensuring that the CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 can withstand the demands of harsh environments and extended usage. The devices also incorporate features such as high-speed data ports, which facilitate bidirectional data flow, making them optimal for both read and write operations.

In summary, the CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 SRAMs by Cypress are excellent choices for those seeking high-performance, low-power memory solutions. Their advanced technology, combined with a variety of features and options, caters to the needs of many industries, paving the way for innovative designs in modern electronics.
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